Datasheet

LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 57 of 155
NXP Semiconductors
LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
Debug pins
DBGEN L4 K4 A6 28
[2]
I; PU I JTAG interface control signal. Also used for boundary scan. To
use the part in functional mode, connect this pin in one of the
following ways:
• Leave DBGEN open. The DBGEN pin is pulled up
internally by a 50 kΩ resistor.
• Tie DBGEN to VDDIO.
• Pull DBGEN up to VDDIO with an external pull-up resistor.
TCK/SWDCLK J5 G5 H2 27
[2]
I; F I Test Clock for JTAG interface (default) or Serial Wire (SW)
clock.
TRST
M4 L4 B4 29
[2]
I; PU I Test Reset for JTAG interface.
TMS/SWDIO K6 K5 C4 30
[2]
I; PU I Test Mode Select for JTAG interface (default) or SW debug
data input/output.
TDO/SWO K5 J5 H3 31
[2]
O O Test Data Out for JTAG interface (default) or SW trace output.
TDI J4 H4 G3 26
[2]
I; PU I Test Data In for JTAG interface.
USB0 pins
USB0_DP F2 E2 E1 18
[6]
- I/O USB0 bidirectional D+ line.
USB0_DM G2 F2 E2 20
[6]
- I/O USB0 bidirectional D line.
USB0_VBUS F1 E1 E3 21
[6]
[7]
- I/O VBUS pin (power on USB cable). This pin includes an internal
pull-down resistor of 64 kΩ (typical)  16 kΩ.
USB0_ID H2 G2 F1 22
[8]
- I Indicates to the transceiver whether connected as an A-device
(USB0_ID LOW) or B-device (USB0_ID HIGH). For OTG this
pin has an internal pull-up resistor.
USB0_RREF H1 G1 F3 24
[8]
- 12.0 kΩ (accuracy 1 %) on-board resistor to ground for current
reference.
USB1 pins
USB1_DP F12 D11 E9 89
[9]
- I/O USB1 bidirectional D+ line.
USB1_DM G12 E11 E10 90
[9]
- I/O USB1 bidirectional D line.
I
2
C-bus pins
I2C0_SCL L15 K13 D6 92
[10]
I; F I/O I
2
C clock input/output. Open-drain output (for I
2
C-bus
compliance).
I2C0_SDA L16 K14 E6 93
[10]
I; F I/O I
2
C data input/output. Open-drain output (for I
2
C-bus
compliance).
Reset and wake-up pins
RESET
D9 C7 B6 128
[11]
I; IA I External reset input: A LOW-going pulse as short as 50 ns on
this pin resets the device, causing I/O ports and peripherals to
take on their default states, and processor execution to begin
at address 0. This pin does not have an internal pull-up.
WAKEUP0 A9 A9 A4 130
[11]
I; IA I External wake-up input; can raise an interrupt and can cause
wake-up from any of the low-power modes. A pulse with a
duration > 45 ns wakes up the part. This pin does not have an
internal pull-up.
Table 3. Pin description
…continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256 TFBGA180 TFBGA100 LQFP144 Reset state [1] Type
Description