Datasheet

LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 6 of 155
NXP Semiconductors
LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
5. Block diagram
(1) Not available on all parts (see Tab le 2 ).
Fig 1. LPC4350/30/20/10 Block diagram
ARM
CORTEX-M4
TEST/DEBUG
INTERFACE
I-code bus D-code bus system bus
DMA LCD
(1)
SD/
MMC
ETHERNET
(1)
10/100
MAC
IEEE 1588
HIGH-SPEED
USB0
(1)
HOST/
DEVICE/OTG
HIGH-SPEED
USB1
(1)
HOST/DEVICE
EMC
HIGH-SPEED PHY
32 kB AHB SRAM
16 +16 kB AHB SRAM
SPIFI
AES ENCRYPTION/
DECRYPTION
(2)
HS GPIO
SPI
SGPIO
SCT
64 kB ROM
I
2
C0
I
2
S0
I
2
S1
C_CAN1
MOTOR
CONTROL
PWM
(1)
TIMER3
TIMER2
USART2
USART3
SSP1
RI TIMER
QEI
(1)
GIMA
BRIDGE 0 BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE
BRIDGE
AHB MULTILAYER MATRIX
LPC4350/30/20/20/10
128 kB LOCAL SRAM
72 kB LOCAL SRAM
10-bit ADC0
10-bit ADC1
C_CAN0
I
2
C1
10-bit DAC
BRIDGE
RGU
CCU2
CGU
CCU1
ALARM TIMER
CONFIGURATION
REGISTERS
OTP MEMORY
EVENT ROUTER
POWER MODE CONTROL
12 MHz IRC
RTC POWER DOMAIN
BACKUP REGISTERS
RTC OSC
RTC
002aaf772
slaves
slaves
masters
ARM
CORTEX-M0
TEST/DEBUG
INTERFACE
= connected to GPDMA
GPIO
INTERRUPTS
GPIO GROUP0
INTERRUPT
GPIO GROUP1
INTERRUPT
WWDT
USART0
UART1
SSP0
TIMER0
TIMER1
SCU