Datasheet

LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 62 of 155
NXP Semiconductors
LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
7.5 AHB multilayer matrix
7.6 Nested Vectored Interrupt Controller (NVIC)
The NVIC is an integral part of the Cortex-M4. The tight coupling to the CPU allows for low
interrupt latency and efficient processing of late arriving interrupts.
The ARM Cortex-M0 co-processor has its own NVIC with 32 vectored interrupts. Most
peripheral interrupts are shared between the Cortex-M0 and Cortex-M4 NVICs.
Fig 6. AHB multilayer matrix master and slave connections
ARM
CORTEX-M4
TEST/DEBUG
INTERFACE
ARM
CORTEX-M0
TEST/DEBUG
INTERFACE
DMA ETHERNET USB1USB0 LCD
SD/
MMC
EXTERNAL
MEMORY
CONTROLLER
APB, RTC
DOMAIN
PERIPHERALS
16 kB + 16 kB
AHB SRAM
64 kB ROM
128 kB LOCAL SRAM
72 kB LOCAL SRAM
System
bus
I-
code
bus
D-
code
bus
masters
slaves
01
AHB MULTILAYER MATRIX
= master-slave connection
32 kB AHB SRAM
SPIFI
SGPIO
AHB PERIPHERALS
REGISTER
INTERFACES
002aaf873
HIGH-SPEED PHY