Datasheet
LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 65 of 155
NXP Semiconductors
LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
[1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.
Remark: Pin functions for SPIFI and SSP0 boot are different.
[1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.
Remark: Pin functions for SPIFI and SSP0 boot are different.
7.13 Memory mapping
The memory map shown in Figure 7 and Figure 8 is global to both the Cortex-M4 and the
Cortex-M0 processors and all SRAM is shared between both processors. Each processor
uses its own ARM private bus memory map for the NVIC and other system functions.
EMC 16-bit 0 1 0 0 Boot from external static memory (such as NOR
flash) using CS0 and a 16-bit data bus.
EMC 32-bit 0 1 0 1 Boot from external static memory (such as NOR
flash) using CS0 and a 32-bit data bus.
USB0011 0Boot from USB0.
USB1011 1Boot from USB1.
SPI (SSP) 1 0 0 0 Boot from SPI flash connected to the SSP0
interface on P3_3 (function SSP0_SCK), P3_6
(function SSP0_SSEL), P3_7 (function
SSP0_MISO), and P3_8 (function SSP0_MOSI)
[1]
.
USART3 1 0 0 1 Boot from device connected to USART3 using pins
P2_3 and P2_4.
Table 4. Boot mode when OTP BOOT_SRC bits are programmed
…continued
Boot mode BOOT_SRC
bit 3
BOOT_SRC
bit 2
BOOT_SRC
bit 1
BOOT_SRC
bit 0
Description
Table 5. Boot mode when OPT BOOT_SRC bits are zero
Boot mode Pins Description
P2_9 P2_8 P1_2 P1_1
USART0 LOW LOW LOW LOW Boot from device connected to USART0 using pins
P2_0 and P2_1.
SPIFI LOW LOW LOW HIGH Boot from Quad SPI flash connected to the SPIFI
interface on P3_3 to P3_8
[1]
.
EMC 8-bit LOW LOW HIGH LOW Boot from external static memory (such as NOR
flash) using CS0 and an 8-bit data bus.
EMC 16-bit LOW LOW HIGH HIGH Boot from external static memory (such as NOR
flash) using CS0 and a 16-bit data bus.
EMC 32-bit LOW HIGH LOW LOW Boot from external static memory (such as NOR
flash) using CS0 and a 32-bit data bus.
USB0 LOW HIGH LOW HIGH Boot from USB0
USB1 LOW HIGH HIGH LOW Boot from USB1.
SPI (SSP) LOW HIGH HIGH HIGH Boot from SPI flash connected to the SSP0
interface on P3_3 (function SSP0_SCK), P3_6
(function SSP0_SSEL), P3_7 (function
SSP0_MISO), and P3_8 (function SSP0_MOSI)
[1]
.
USART3 HIGH LOW LOW LOW Boot from device connected to USART3 using pins
P2_3 and P2_4.