Datasheet

Product data sheet Rev. 4.2 — 18 August 2014 84 of 155

NXP Semiconductors

LPC4350/30/20/10

32-bit ARM Cortex-M4/M0 microcontroller

Active mode and sleep mode apply to the state of the core. In a dual-core system, either

core can be in active or sleep mode independently of the other core.

If the core is in Active mode, it is fully operational and can access peripherals and

memories as configured by software. If the core is in Sleep mode, it receives no clocks,

but peripherals and memories remain running.

Either core can enter sleep mode from active mode independently of the other core and

while the other core remains in active mode or is in sleep mode.

Power-down modes apply to the entire system. In the Power-down modes, both cores and

all peripherals except for peripherals in the always-on power domain are shut down.

Memories can remain powered for retaining memory contents as defined by the individual

power-down mode.

Either core in active mode can put the part into one of the three power down modes if the

core is enabled to do so. If both cores are enabled for putting the system into power-down,

then the system enters power-down only once both cores have received a WFI or WFE

instruction.

Wake-up from sleep mode is caused by an interrupt or event in the core’s NVIC. The

interrupt is captured in the NVIC and an event is captured in the Event router. Both cores

can wake up from sleep mode independently of each other.

Wake-up from the Power-down modes, Deep-sleep, Power-down, and Deep power-down,

is caused by an event on the WAKEUP pins or an event from the RTC or alarm timer.

When waking up from Deep power-down mode, the part resets and attempts to boot.

7.23 Serial Wire Debug/JTAG

Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and

trace functions are supported in addition to a standard JTAG debug and parallel trace

functions. The ARM Cortex-M4 is configured to support up to eight breakpoints and four

watch points.

Remark: Serial Wire Debug is supported for the ARM Cortex-M4 only,

The ARM Cortex-M0 coprocessor supports JTAG debug. A standard ARM

Cortex-compliant debugger can debug the ARM Cortex-M4 and the ARM Cortex-M0

cores separately or both cores simultaneously.

Remark: In order to debug the ARM Cortex-M0, release the M0 reset by software in the

RGU block.