Datasheet

LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.2 — 18 August 2014 94 of 155
NXP Semiconductors
LPC4350/30/20/10
32-bit ARM Cortex-M4/M0 microcontroller
[3] Pin VPP should either be not connected (when OTP does not need to be programmed) or tied to pins VDDIO and VDDREG to ensure
the same ramp-up time for both supply voltages.
[4] V
DD(REG)(3V3)
= 3.3 V; V
DD(IO)
= 3.3 V; T
amb
=25C.
[5] PLL1 disabled; IRC running; CCLK = 12 MHz.
[6] V
BAT
= 3.6 V.
[7] V
DD(IO)
= V
DDA
= 3.6 V; over entire frequency range CCLK = 12 MHz to 180 MHz.
[8] On pin VBAT; T
amb
=25C.
[9] V
DD(REG)(3V3)
= 3.3 V; V
DD(IO)
= 3.3 V. Input leakage increases when V
DD(IO)
is floating or grounded. It is recommended to keep
V
DD(REG)(3V3)
and V
DD(IO)
powered in deep power-down mode.
[10] V
ps
corresponds to the output of the power switch (see Figure 9) which is determined by the greater of V
BAT
and V
DD(Reg)(3V3)
.
[11] V
DDA(3V3)
= 3.3 V; T
amb
=25C.
[12] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[13] To V
SS
.
[14] The values specified are simulated and absolute values.
[15] The weak pull-up resistor is connected to the V
DD(IO)
rail and pulls up the I/O pin to the V
DD(IO)
level.
[16] The input cell disables the weak pull-up resistor when the applied input voltage exceeds V
DD(IO)
.
[17] The parameter value specified is a simulated value excluding bond capacitance.
[18] For USB operation 3.0 V  V
DD((IO)
 3.6 V. Guaranteed by design.
[19] V
DD(IO)
present.
[20] Includes external resistors of 33 1 % on D+ and D.