Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LBGA 256 (17x17) 32-Bit Dual-Core 204 MHz I/O number 164

1. General description

The LPC435x/3x/2x/1x are ARM Cortex-M4 based microcontrollers for embedded

applications which include an ARM Cortex-M0 coprocessor, up to 1 MB of flash and

136 kB of on-chip SRAM, 16 kB of EEPROM memory, a quad SPI Flash Interface (SPIFI),

advanced configurable peripherals such as the State Configurable Timer (SCT) and the

Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers, Ethernet,

LCD, an external memory controller, and multiple digital and analog peripherals. The

LPC435x/3x/2x/1x operate at CPU frequencies of up to 204 MHz.

The ARM Cortex-M4 is a next generation 32-bit core that offers system enhancements

such as low power consumption, enhanced debug features, and a high level of support

block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a

Harvard architecture with separate local instruction and data buses as well as a third bus

for peripherals, and includes an internal prefetch unit that supports speculative branching.

The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD

instructions. A hardware floating-point unit is integrated in the core.

The ARM Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core which

is upward code- and tool-compatible with the Cortex-M4 core. The Cortex-M0

coprocessor, designed as a replacement for existing 8/16-bit microcontrollers, offers up to

204 MHz performance with a simple instruction set and reduced code size.

For additional documentation related to the LPC43xx parts, see Section 17

2. Features and benefits

 Cortex-M4 Processor core

 ARM Cortex-M4 processor (version r0p1), running at frequencies of up to

204 MHz.

 ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions.

 ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).

 Hardware floating-point unit.

 Non-maskable Interrupt (NMI) input.

 JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch

points.

 Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.

 System tick timer.

 Cortex-M0 Processor core

 ARM Cortex-M0 co-processor (version r0p0) capable of off-loading the main ARM

Cortex-M4 application processor.

LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 MCU; up to 1 MB flash and 136 kB

SRAM; Ethernet, two High-speed USB, LCD, EMC

Rev. 4 — 19 August 2014 Product data sheet

Summary of content (158 pages)

PAGE 1
LPC435x/3x/2x/1x 32-bit ARM Cortex-M4/M0 MCU; up to 1 MB flash and 136 kB SRAM; Ethernet, two High-speed USB, LCD, EMC Rev. 4 — 19 August 2014 Product data sheet 1.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller     LPC435X_3X_2X_1X Product data sheet  Running at frequencies of up to 204 MHz.  JTAG  Built-in NVIC. On-chip memory  Up to 1 MB on-chip dual bank flash memory with flash accelerator.  16 kB on-chip EEPROM data memory.  136 kB SRAM for code and data use.  Multiple SRAM blocks with separate bus access. Two SRAM blocks can be powered down individually.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller     LPC435X_3X_2X_1X Product data sheet  Secure Digital Input Output (SD/MMC) card interface.  Eight-channel General-Purpose DMA controller can access all memories on the AHB and all DMA-capable AHB slaves.  Up to 164 General-Purpose Input/Output (GPIO) pins with configurable pull-up/pull-down resistors.  GPIO registers are located on the AHB for fast access. GPIO ports have DMA support.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller  Available as LQFP208, LQFP144, LBGA256, or TFBGA100 packages. 3. Applications     LPC435X_3X_2X_1X Product data sheet Motor control Power management White goods RFID readers  Embedded audio applications  Industrial automation  e-metering All information provided in this document is subject to legal disclaimers. Rev. 4 — 19 August 2014 © NXP Semiconductors N.V. 2014. All rights reserved.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC4357FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2 LPC4357JET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2 LPC4357JBD208 LQFP208 Plastic low profile quad flat package; 208 leads; body 28  28  1.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 4.1 Ordering options GPIO Temperature range[1] ADC channels QEI PWM USB1 (Host, Device)/ ULPI interface USB0 (Host, Device, OTG) Ethernet LCD Total SRAM Flash bank B Flash total Flash bank A Ordering options Type number Table 2.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 5.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 6. Pinning information 6.1 Pinning LPC435x/3xFET256 ball A1 index area 2 1 4 3 6 5 8 7 10 9 12 11 14 13 ball A1 index area 16 LPC433x/2x/1xFET100 1 15 A 2 3 4 5 6 7 8 A B C B E C D F D G E H J F L G K M H N J P R K T 002aah179 002aah177 Transparent top view Transparent top view Pin configuration TFBGA100 package 108 104 109 LPC4357/53FBD208 Fig 4.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 0 on ADC0 and channel 0 on ADC1, channel 1 inputs (named ADC0_1 and ADC1_1) are tied together and connected to channel 1 on ADC0 and ADC1, and so forth. There are eight ADC channels total for the two ADCs. LPC435X_3X_2X_1X Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4 — 19 August 2014 © NXP Semiconductors N.V. 2014. All rights reserved.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Type 32 Description [1] 47 Reset state LQFP144 LBGA256 Pin name LQFP208 Pin description TFBGA100 Table 3. Multiplexed digital pins P0_0 P0_1 L3 M2 G2 G1 50 34 [2] [2] N; PU N; PU I/O GPIO0[0] — General purpose digital input/output pin. I/O SSP1_MISO — Master In Slave Out for SSP1. I ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface). I/O SGPIO0 — General purpose digital input/output pin.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P1_2 P1_3 P1_4 LQFP144 K2 58 42 R3 P5 T3 LPC435X_3X_2X_1X Product data sheet K1 J1 J2 60 61 64 43 44 47 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 R2 Description [1] TFBGA100 P1_1 LBGA256 Pin name Reset state Table 3. I/O GPIO0[8] — General purpose digital input/output pin. Boot pin (see Table 5). O CTOUT_7 — SCT output 7. Match output 3 of timer 1.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P1_6 P1_7 LQFP144 J4 65 48 T4 T5 K4 G4 67 69 49 50 [2] [2] [2] N; PU N; PU N; PU Type LQFP208 R5 Description [1] TFBGA100 P1_5 LBGA256 Pin name Reset state Table 3. I/O GPIO1[8] — General purpose digital input/output pin. O CTOUT_10 — SCT output 10. Match output 3 of timer 3. - R — Function reserved. O EMC_CS0 — LOW active Chip Select 0 signal.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P1_9 P1_10 P1_11 LQFP144 H5 71 51 T7 R8 T9 LPC435X_3X_2X_1X Product data sheet J5 H6 J7 73 75 77 52 53 55 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 R7 Description [1] TFBGA100 P1_8 LBGA256 Pin name Reset state Table 3. I/O GPIO1[1] — General purpose digital input/output pin. O U1_DTR — Data Terminal Ready output for UART1.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P1_13 P1_14 P1_15 LQFP144 K7 78 56 R10 R11 T12 LPC435X_3X_2X_1X Product data sheet H8 J8 K8 83 85 87 60 61 62 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 R9 Description [1] TFBGA100 P1_12 LBGA256 Pin name Reset state Table 3. I/O GPIO1[5] — General purpose digital input/output pin. I U1_DCD — Data Carrier Detect input for UART1.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P1_17 P1_18 P1_19 LQFP144 H9 90 64 M8 N12 M11 LPC435X_3X_2X_1X Product data sheet H10 J10 K9 93 95 96 66 67 68 [2] [3] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 M7 Description [1] TFBGA100 P1_16 LBGA256 Pin name Reset state Table 3. I/O GPIO0[3] — General purpose digital input/output pin. I U2_RXD — Receiver input for USART2.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P2_0 LQFP144 K10 100 70 T16 G10 108 75 [2] [2] N; PU N; PU Type LQFP208 M10 Description [1] TFBGA100 P1_20 LBGA256 Pin name Reset state Table 3. I/O GPIO0[15] — General purpose digital input/output pin. I/O SSP1_SSEL — Slave Select for SSP1. - R — Function reserved. O ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface). I T0_CAP2 — Capture input 2 of timer 0.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P2_3 LQFP144 F5 121 84 J12 D8 127 87 [2] [3] N; PU N; PU Type LQFP208 M15 Description [1] TFBGA100 P2_2 LBGA256 Pin name Reset state Table 3. I/O SGPIO6 — General purpose digital input/output pin. I/O U0_UCLK — Serial clock input/output for USART0 in synchronous mode. I/O EMC_A11 — External memory address line 11. O USB0_IND1 — USB0 port indicator LED control output 1.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued LQFP144 D10 131 91 [3] N; PU Type LQFP208 K14 Description [1] TFBGA100 P2_5 LBGA256 Pin name Reset state Table 3. I/O SGPIO14 — General purpose digital input/output pin. I CTIN_2 — SCT input 2. Capture input 2 of timer 0. I USB1_VBUS — Monitors the presence of USB1 bus power. Note: This signal must be HIGH for USB reset to occur.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P2_10 P2_11 P2_12 LQFP144 B10 144 102 G16 F16 E15 LPC435X_3X_2X_1X Product data sheet E8 A9 B9 146 148 153 104 105 106 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 H16 Description [1] TFBGA100 P2_9 LBGA256 Pin name Reset state Table 3. I/O GPIO1[10] — General purpose digital input/output pin. Boot pin (see Table 5). O CTOUT_3 — SCT output 3.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P3_0 P3_1 LQFP144 A10 156 108 F13 G11 LPC435X_3X_2X_1X Product data sheet A8 F7 161 163 112 114 [2] [2] [2] N; PU N; PU N; PU Type LQFP208 C16 Description [1] TFBGA100 P2_13 LBGA256 Pin name Reset state Table 3. I/O GPIO1[13] — General purpose digital input/output pin. I CTIN_4 — SCT input 4. Capture input 2 of timer 1. - R — Function reserved.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P3_3 P3_4 LQFP144 G6 166 116 B14 A15 LPC435X_3X_2X_1X Product data sheet A7 B8 169 171 118 119 [2] [4] [2] OL; PU N; PU N; PU Type LQFP208 F11 Description [1] TFBGA100 P3_2 LBGA256 Pin name Reset state Table 3. I/O I2S0_TX_SDA — I2S transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P3_6 P3_7 P3_8 LQFP144 B7 173 121 B13 C11 C10 LPC435X_3X_2X_1X Product data sheet C7 D7 E7 174 176 179 122 123 124 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 C12 Description [1] TFBGA100 P3_5 LBGA256 Pin name Reset state Table 3. I/O GPIO1[15] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P4_1 P4_2 P4_3 LQFP144 - 1 1 A1 D3 C2 LPC435X_3X_2X_1X Product data sheet - - - 3 12 10 3 8 7 [2] [5] [2] [5] N; PU N; PU N; PU N; PU Type LQFP208 D5 Description [1] TFBGA100 P4_0 LBGA256 Pin name Reset state Table 3. I/O GPIO2[0] — General purpose digital input/output pin. O MCOA0 — Motor control PWM channel 0, output A.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P4_5 P4_6 LQFP144 - 14 9 D2 C1 LPC435X_3X_2X_1X Product data sheet - - 15 17 10 11 [5] [2] [2] N; PU N; PU N; PU Type LQFP208 B1 Description [1] TFBGA100 P4_4 LBGA256 Pin name Reset state Table 3. I/O GPIO2[4] — General purpose digital input/output pin. O CTOUT_2 — SCT output 2. Match output 2 of timer 0. O LCD_VD1 — LCD data. - R — Function reserved.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P4_8 P4_9 P4_10 LQFP144 - 21 14 E2 L2 M3 LPC435X_3X_2X_1X Product data sheet - - - 23 48 51 15 33 35 [2] [2] [2] [2] O; PU N; PU N; PU N; PU Type LQFP208 H4 Description [1] TFBGA100 P4_7 LBGA256 Pin name Reset state Table 3. O LCD_DCLK — LCD panel clock. I GP_CLKIN — General purpose clock input to the CGU. - R — Function reserved. - R — Function reserved.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P5_1 P5_2 P5_3 LQFP144 - 53 37 P3 R4 T8 LPC435X_3X_2X_1X Product data sheet - - - 55 63 76 39 46 54 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 N3 Description [1] TFBGA100 P5_0 LBGA256 Pin name Reset state Table 3. I/O GPIO2[9] — General purpose digital input/output pin. O MCOB2 — Motor control PWM channel 2, output B.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P5_5 P5_6 P5_7 LQFP144 - 80 57 P10 T13 R12 LPC435X_3X_2X_1X Product data sheet - - - 81 89 91 58 63 65 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 P9 Description [1] TFBGA100 P5_4 LBGA256 Pin name Reset state Table 3. I/O GPIO2[13] — General purpose digital input/output pin. O MCOB0 — Motor control PWM channel 0, output B.
PAGE 28
LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P6_1 P6_2 LQFP144 H7 105 73 R15 L13 LPC435X_3X_2X_1X Product data sheet G5 J9 107 111 74 78 [2] [2] [2] N; PU N; PU N; PU Type LQFP208 M12 Description [1] TFBGA100 P6_0 LBGA256 Pin name Reset state Table 3. - R — Function reserved. O I2S0_RX_MCLK — I2S receive master clock. - R — Function reserved. - R — Function reserved. I/O I2S0_RX_SCK — Receive Clock.
PAGE 29
LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued LQFP144 - 113 79 [2] N; PU Type LQFP208 P15 Description [1] TFBGA100 P6_3 LBGA256 Pin name Reset state Table 3. I/O GPIO3[2] — General purpose digital input/output pin. O USB0_PPWR — VBUS drive signal (towards external charge pump or power management unit); indicates that the VBUS signal must be driven (active HIGH). Add a pull-down resistor to disable the power switch at reset.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P6_8 P6_9 P6_10 LQFP144 - 123 85 H13 J15 H15 LPC435X_3X_2X_1X Product data sheet - F8 - 125 139 142 86 97 100 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 J13 Description [1] TFBGA100 P6_7 LBGA256 Pin name Reset state Table 3. - R — Function reserved. I/O EMC_A15 — External memory address line 15.
PAGE 31
LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P6_12 P7_0 P7_1 LQFP144 C9 143 101 G15 B16 C14 LPC435X_3X_2X_1X Product data sheet - - - 145 158 162 103 110 113 [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 H12 Description [1] TFBGA100 P6_11 LBGA256 Pin name Reset state Table 3. I/O GPIO3[7] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved.
PAGE 32
LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P7_3 P7_4 P7_5 LQFP144 - 165 115 C13 C8 A7 LPC435X_3X_2X_1X Product data sheet - - - 167 189 191 117 132 133 [2] [2] [5] [5] N; PU N; PU N; PU N; PU Type LQFP208 A16 Description [1] TFBGA100 P7_2 LBGA256 Pin name Reset state Table 3. I/O GPIO3[10] — General purpose digital input/output pin. I CTIN_4 — SCT input 4. Capture input 2 of timer 1.
PAGE 33
LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P7_7 P8_0 P8_1 LQFP144 - 194 134 B6 E5 H5 LPC435X_3X_2X_1X Product data sheet - - - 201 2 34 140 - - [2] [5] [3] [3] N; PU N; PU N; PU N; PU Type LQFP208 C7 Description [1] TFBGA100 P7_6 LBGA256 Pin name Reset state Table 3. I/O GPIO3[14] — General purpose digital input/output pin. O CTOUT_11 — SCT output 1. Match output 3 of timer 2.
PAGE 34
LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P8_3 P8_4 P8_5 LQFP144 - 36 - J3 J2 J1 LPC435X_3X_2X_1X Product data sheet - - - 37 39 40 - - - [3] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 K4 Description [1] TFBGA100 P8_2 LBGA256 Pin name Reset state Table 3. I/O GPIO4[2] — General purpose digital input/output pin. O USB0_IND0 — USB0 port indicator LED control output 0. - R — Function reserved.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P8_7 P8_8 P9_0 LQFP144 - 43 - K1 L1 T1 LPC435X_3X_2X_1X Product data sheet - - - 45 49 59 - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 K3 Description [1] TFBGA100 P8_6 LBGA256 Pin name Reset state Table 3. I/O GPIO4[6] — General purpose digital input/output pin. I USB1_ULPI_NXT — ULPI link NXT signal. Data flow control signal from the PHY.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued P9_2 P9_3 P9_4 LQFP144 - 66 - N8 M6 N10 LPC435X_3X_2X_1X Product data sheet - - - 70 79 92 - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 N6 Description [1] TFBGA100 P9_1 LBGA256 Pin name Reset state Table 3. I/O GPIO4[13] — General purpose digital input/output pin. O MCOA2 — Motor control PWM channel 2, output A. - R — Function reserved.
PAGE 37
LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued LQFP144 - 98 69 [2] N; PU Type LQFP208 M9 Description [1] TFBGA100 P9_5 LBGA256 Pin name Reset state Table 3. - R — Function reserved. O MCOA1 — Motor control PWM channel 1, output A. O USB1_PPWR — VBUS drive signal (towards external charge pump or power management unit); indicates that VBUS must be driven (active high).
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued PA_3 PA_4 PB_0 LQFP144 - 136 - H11 G13 B15 LPC435X_3X_2X_1X Product data sheet - - - 147 151 164 - - - [3] [3] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 K15 Description [1] TFBGA100 PA_2 LBGA256 Pin name Reset state Table 3. I/O GPIO4[9] — General purpose digital input/output pin. I QEI_PHB — Quadrature Encoder Interface PHB input.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued PB_2 PB_3 PB_4 LQFP144 - 175 - B12 A13 B11 LPC435X_3X_2X_1X Product data sheet - - - 177 178 180 - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 A14 Description [1] TFBGA100 PB_1 LBGA256 Pin name Reset state Table 3. - R — Function reserved. I USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP data line direction. O LCD_VD22 — LCD data.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued PB_6 PC_0 PC_1 LQFP144 - 181 - A6 D4 E4 LPC435X_3X_2X_1X Product data sheet - - - - 7 9 - - - [2] [5] [5] [2] N; PU N; PU N; PU N; PU Type LQFP208 A12 Description [1] TFBGA100 PB_5 LBGA256 Pin name Reset state Table 3. - R — Function reserved. I/O USB1_ULPI_D4 — ULPI link bidirectional data line 4. O LCD_VD14 — LCD data. - R — Function reserved.
PAGE 41
LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued PC_3 PC_4 LQFP144 - 13 - F5 F4 - - 11 16 - - [2] [5] [2] N; PU N; PU N; PU Type LQFP208 F6 Description [1] TFBGA100 PC_2 LBGA256 Pin name Reset state Table 3. I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6. - R — Function reserved. I U1_CTS — Clear to Send input for UART 1. O ENET_TXD2 — Ethernet transmit data 2 (MII interface).
PAGE 42
LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued PC_7 PC_8 PC_9 LQFP144 - 22 - G5 N4 K2 LPC435X_3X_2X_1X Product data sheet - - - - - - - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 H6 Description [1] TFBGA100 PC_6 LBGA256 Pin name Reset state Table 3. - R — Function reserved. I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2. - R — Function reserved.
PAGE 43
LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued PC_11 PC_12 PC_13 LQFP144 - - - L5 L6 M1 LPC435X_3X_2X_1X Product data sheet - - - - - - - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 M5 Description [1] TFBGA100 PC_10 LBGA256 Pin name Reset state Table 3. - R — Function reserved. O USB1_ULPI_STP — ULPI link STP signal. Asserted to end or interrupt transfers to the PHY.
PAGE 44
LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued PD_0 PD_1 PD_2 LQFP144 - - - N2 P1 R1 LPC435X_3X_2X_1X Product data sheet - - - - - - - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 N1 Description [1] TFBGA100 PC_14 LBGA256 Pin name Reset state Table 3. - R — Function reserved. - R — Function reserved. I U1_RXD — Receiver input for UART 1. - R — Function reserved.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued PD_4 PD_5 PD_6 LQFP144 - - - T2 P6 R6 LPC435X_3X_2X_1X Product data sheet - - - - - 68 - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 P4 Description [1] TFBGA100 PD_3 LBGA256 Pin name Reset state Table 3. - R — Function reserved. O CTOUT_6 — SCT output 7. Match output 2 of timer 1. I/O EMC_D17 — External memory data line 17.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued PD_8 PD_9 PD_10 LQFP144 - 72 - P8 T11 P11 LPC435X_3X_2X_1X Product data sheet - - - 74 84 86 - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 T6 Description [1] TFBGA100 PD_7 LBGA256 Pin name Reset state Table 3. - R — Function reserved. I CTIN_5 — SCT input 5. Capture input 2 of timer 2. I/O EMC_D21 — External memory data line 21.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued PD_12 PD_13 PD_14 LQFP144 - 88 - N11 T14 R13 LPC435X_3X_2X_1X Product data sheet - - - 94 97 99 - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 N9 Description [1] TFBGA100 PD_11 LBGA256 Pin name Reset state Table 3. - R — Function reserved. - R — Function reserved. O EMC_CS3 — LOW active Chip Select 3 signal. - R — Function reserved.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued PD_16 PE_0 PE_1 LQFP144 - 101 - R14 P14 N14 LPC435X_3X_2X_1X Product data sheet - - - 104 106 112 - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 T15 Description [1] TFBGA100 PD_15 LBGA256 Pin name Reset state Table 3. - R — Function reserved. - R — Function reserved. I/O EMC_A17 — External memory address line 17. - R — Function reserved.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued PE_3 PE_4 PE_5 LQFP144 - 115 - K12 K13 N16 LPC435X_3X_2X_1X Product data sheet - - - 118 120 122 - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 M14 Description [1] TFBGA100 PE_2 LBGA256 Pin name Reset state Table 3. I ADCTRIG0 — ADC trigger input 0. I CAN0_RD — CAN receiver input. - R — Function reserved.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued PE_7 PE_8 PE_9 LQFP144 - 124 - F15 F14 E16 LPC435X_3X_2X_1X Product data sheet - - - 149 150 152 - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 M16 Description [1] TFBGA100 PE_6 LBGA256 Pin name Reset state Table 3. - R — Function reserved. O CTOUT_2 — SCT output 2. Match output 2 of timer 0. I U1_RI — Ring Indicator input for UART 1.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued PE_11 PE_12 PE_13 LQFP144 - 154 - D16 D15 G14 LPC435X_3X_2X_1X Product data sheet - - - - - - - - - [2] [2] [2] [2] N; PU N; PU N; PU N; PU Type LQFP208 E14 Description [1] TFBGA100 PE_10 LBGA256 Pin name Reset state Table 3. - R — Function reserved. I CTIN_3 — SCT input 3. Capture input 1 of timer 1. O U1_DTR — Data Terminal Ready output for UART 1.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued PE_15 PF_0 PF_1 LQFP144 - - - E13 D12 E11 LPC435X_3X_2X_1X Product data sheet - - - - 159 - - - - [2] [2] [2] [2] N; PU N; PU O; PU N; PU Type LQFP208 C15 Description [1] TFBGA100 PE_14 LBGA256 Pin name Reset state Table 3. - R — Function reserved. - R — Function reserved. - R — Function reserved. O EMC_DYCS3 — SDRAM chip select 3.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued PF_3 PF_4 PF_5 LQFP144 - 168 - E10 D10 E9 LPC435X_3X_2X_1X Product data sheet - H4 - 170 172 190 - 120 - [2] [2] [2] [5] N; PU N; PU O; PU N; PU Type LQFP208 D11 Description [1] TFBGA100 PF_2 LBGA256 Pin name Reset state Table 3. - R — Function reserved. O U3_TXD — Transmitter output for USART3. I/O SSP0_MISO — Master In Slave Out for SSP0.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued PF_7 PF_8 LQFP144 - 192 - B7 E6 LPC435X_3X_2X_1X Product data sheet - - 193 - - - [5] [5] [5] N; PU N; PU N; PU Type LQFP208 E7 Description [1] TFBGA100 PF_6 LBGA256 Pin name Reset state Table 3. - R — Function reserved. I/O U3_DIR — RS-485/EIA-485 output enable/direction control for USART3. I/O SSP1_MISO — Master In Slave Out for SSP1.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued PF_10 PF_11 LQFP144 - 203 - A3 A2 LPC435X_3X_2X_1X Product data sheet - - 205 207 - - [5] [5] [5] N; PU N; PU N; PU Type LQFP208 D6 Description [1] TFBGA100 PF_9 LBGA256 Pin name Reset state Table 3. - R — Function reserved. I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. O CTOUT_1 — SCT output 1. Match output 3 of timer 3.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued LQFP208 LQFP144 K3 62 45 Type TFBGA100 N5 Description [1] LBGA256 Pin name Reset state Table 3. Clock pins CLK0 CLK1 CLK2 CLK3 T10 D14 P12 LPC435X_3X_2X_1X Product data sheet - K6 - - 141 - - 99 - [4] [4] [4] [4] O; PU O; PU O; PU O; PU O EMC_CLK0 — SDRAM clock 0. O CLKOUT — Clock output pin. - R — Function reserved. - R — Function reserved.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued LQFP208 LQFP144 A6 41 28 Type TFBGA100 L4 Description [1] LBGA256 Pin name Reset state Table 3. Debug pins DBGEN [2] I I JTAG interface control signal. Also used for boundary scan. To use the part in functional mode, connect this pin in one of the following ways: • Leave DBGEN open. The DBGEN pin is pulled up internally by a 50 kΩ resistor. • • Tie DBGEN to VDDIO.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued LQFP144 A4 187 130 [11] I; IA Type LQFP208 A9 Description [1] TFBGA100 WAKEUP0 LBGA256 Pin name Reset state Table 3. I External wake-up input; can raise an interrupt and can cause wake-up from any of the low power modes. A pulse with a duration of at least 45 ns wakes up the part. Input 0 of the event monitor.No internal pull-up is enabled when this pin is configured as input.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Pin description …continued LQFP144 C1 19 13 [8] Type LQFP208 E1 Description [1] TFBGA100 XTAL2 LBGA256 Pin name Reset state Table 3. - O Output from the oscillator amplifier. Power and ground pins USB0_VDDA 3V3_DRIVER F3 D1 24 16 - - Separate analog 3.3 V power supply for driver. USB0 _VDDA3V3 G3 D2 25 17 - - USB 3.3 V separate power supply voltage.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller - [13] - - Ground. C4, D13, G6, G7, G8, H8, H9, J8, J9, K9, K10, M13, P7, P13 5, 56, 109, 157 4, 40, 76, 109 [13] - - Ground. B2 196 135 - - Analog ground. G9, H7, J10, J11, K8 VSSIO VSSA C8, D4, D5, G8, J3, J6 C2 Type - VSS [1] LQFP144 Description LQFP208 LBGA256 Pin name Reset state Pin description …continued TFBGA100 Table 3.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7. Functional description 7.1 Architectural overview The ARM Cortex-M4 includes three AHB-Lite buses: the system bus, the I-CODE bus, and the D-code bus. The I-CODE and D-code core buses allow for concurrent code and data accesses from different slave ports.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.6.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Remark: Any interrupt can wake up the ARM Cortex-M4 from sleep mode if enabled in the NVIC. 7.9 Global Input Multiplexer Array (GIMA) The GIMA allows to route signals to event-driven peripheral targets like the SCT, timers, event router, or the ADCs. 7.9.1 Features • • • • • Single selection of a source. Signal inversion. Can capture a pulse if the input event source is faster than the target clock.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Several boot modes are available if P2_7 is LOW on reset depending on the values of the OTP bits BOOT_SRC. If the OTP memory is not programmed or the BOOT_SRC bits are all zero, the boot mode is determined by the states of the boot pins P2_9, P2_8, P1_2, and P1_1. Table 4.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 5. Boot mode when OPT BOOT_SRC bits are zero Boot mode Pins Description P2_9 P2_8 P1_2 P1_1 USB1 LOW HIGH HIGH LOW Boot from USB1. SPI (SSP) LOW HIGH HIGH HIGH Boot from SPI flash connected to the SSP0 interface on P3_3 (function SSP0_SCK), P3_6 (function SSP0_SSEL), P3_7 (function SSP0_MISO), and P3_8 (function SSP0_MOSI)[1]. USART3 HIGH LOW LOW LOW Enter ISP mode using USART3 pins P2_3 and P2_4.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller LPC435x/3x/2x/1x 4 GB 0xFFFF FFFF reserved 0xE010 0000 ARM private bus 0xE000 0000 reserved 0x8800 0000 128 MB SPIFI data 0x8000 0000 256 MB dynamic external memory DYCS3 256 MB dynamic external memory DYCS2 reserved 0x7000 0000 0x6000 0000 0x4400 0000 peripheral bit band alias region reserved 0x4200 0000 0x4010 2000 SGPIO 0x4010 1000 SPI 0x4010 0000 reserved 0x400F 8000 high-speed GPIO 0x400F 4000 reserved 0x
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 0x400E 5000 reserved 0x400E 4000 ADC1 0x400E 3000 ADC0 0x400E 2000 C_CAN0 0x400E 1000 DAC 0x400E
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.15 One-Time Programmable (OTP) memory The OTP provides 64 bit+ 256 bit of memory for general-purpose use. 7.16 General Purpose I/O (GPIO) The LPC435x/3x/2x/1x provide eight GPIO ports with up to 31 GPIO pins each. Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller In the two-counter case, the following operational elements are global to the SCT, but the last three can use match conditions from either counter: • • • • • 7.17.1.1 Clock selection Inputs Events Outputs Interrupts Features • • • • • Two 16-bit counters or one 32-bit counter. Counters clocked by bus clock or selected input. Up counters or up-down counters. State variable allows sequencing across multiple counter cycles.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller • Each slice has a 32-bit pattern match filter. 7.18 AHB peripherals 7.18.1 General Purpose DMA The DMA controller allows peripheral-to memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receives.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller After a few commands configure the interface at startup, the entire flash content is accessible as normal memory using byte, halfword, and word accesses by the processor and/or DMA channels. Simple sequences of commands handle erasing and programming.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 6. 7.18.4.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.18.5 High-speed USB Host/Device/OTG interface (USB0) Remark: USB0 is available on the following parts: LPC435x, LPC433x, LPC432x. USB0 is not available on the LPC431x parts. The USB OTG module allows the LPC435x/3x/2x/1x to connect directly to a USB Host such as a PC (in device mode) or to a USB Device in host mode. 7.18.5.1 Features • • • • • • • • • • • • Contains UTMI+ compliant high-speed transceiver (PHY).
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller The LCD controller provides all of the necessary control signals to interface directly to various color and monochrome LCD panels. Both STN (single and dual panel) and TFT panels can be operated. The display resolution is selectable and can be up to 1024  768 pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller • Supports both full-duplex and half-duplex operation – Supports CSMA/CD Protocol for half-duplex operation. – Supports IEEE 802.3x flow control for full-duplex operation. – Optional forwarding of received pause control frames to the user application in full-duplex operation. – Back-pressure support for half-duplex operation.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.19.2.1 Features • • • • • Maximum UART data bit rate of 8 MBit/s. 16 B Receive and Transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller • Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses • • • • • Synchronous serial communication Master or slave operation 8-frame FIFOs for both transmit and receive 4-bit to 16-bit frame DMA transfers supported by GPDMA 7.19.5 I2C-bus interface Remark: The LPC435x/3x/2x/1x each contain two I2C-bus interfaces.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.19.6.1 Features • The I2S interfaces has separate input/output channels, each of which can operate in master or slave mode. • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. • Mono and stereo audio data supported. • The sampling frequency can range from 16 kHz to 192 kHz (16, 22.05, 32, 44.1, 48, 96, 192) kHz. • Support for an audio master clock.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.20.1.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller • • • • • Uses 32-bit registers for position and velocity. Three position compare registers with interrupts. Index counter for revolution counting. Index compare register with interrupts. Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement. • Digital filter with programmable delays for encoder input signals. • Can accept decoded signal inputs (clk and direction). 7.20.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.21 Analog peripherals 7.21.1 Analog-to-Digital Converter (ADC0/1) Remark: The LPC435x/3x/2x/1x contain two 10-bit ADCs. 7.21.1.1 Features • • • • • • • 10-bit successive approximation analog to digital converter. Input multiplexing among 8 pins. Power-down mode. Measurement range 0 to VDDA. Sampling frequency up to 400 kSamples/s. Burst conversion mode for single or multiple inputs.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller • Alarm interrupt can be generated for a specific date/time. 7.22.1.2 Event monitor/recorder The event monitor/recorder allows recording and creating a time stamp of events related to the WAKEUP pins. Sensors report changes to the state of the WAKEUP pins, and the event monitor/recorder stores records of such events. The event recorder can be powered by the backup battery.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.23.2 System Control Unit (SCU) The system control unit determines the function and electrical mode of the digital pins. By default function 0 is selected for all pins with pull-up enabled. For pins that support a digital and analog function, the ADC function select registers in the SCU enable the analog function.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.23.7 System PLL1 The PLL1 accepts an input clock frequency from an external oscillator in the range of 1 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to 320 MHz.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Wake-up from sleep mode is caused by an interrupt or event in the core’s NVIC. The interrupt is captured in the NVIC and an event is captured in the Event router. Both cores can wake up from sleep mode independently of each other. Wake-up from the Power-down modes, Deep-sleep, Power-down, and Deep power-down, is caused by an event on the WAKEUP pins or an event from the RTC or alarm timer.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller LPC43xx VDDIO to I/O pads to cores VSS REGULATOR to memories, peripherals, oscillators, PLLs VDDREG MAIN POWER DOMAIN ULTRA LOW-POWER REGULATOR VBAT to RTC domain peripherals RESET WAKEUP0/1/2/3 RESET/WAKE-UP CONTROL to RTC I/O pads (Vps) BACKUP REGISTERS RTCX1 RTCX2 32 kHz OSCILLATOR ALARM REAL-TIME CLOCK ALWAYS-ON/RTC POWER DOMAIN DAC VDDA VSSA ADC ADC POWER DOMAIN OTP VPP OTP POWER DOMAIN USB0_VDDA3V_DRIVER U
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller There are three levels of the Code Read Protection: • In level CRP1, access to the chip via the JTAG is disabled. Partial flash updates are allowed (excluding flash sector 0) using a limited set of the ISP commands. This level is useful when CRP is required and flash field updates are needed. CRP1 does prevent the user code from erasing all sectors. • In level CRP2, access to the chip via the JTAG is disabled.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 8. Limiting values Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD(REG)(3V3) regulator supply voltage (3.3 V) on pin VDDREG 0.5 3.6 V VDD(IO) input/output supply voltage on pin VDDIO 0.5 3.6 V VDDA(3V3) analog supply voltage (3.3 V) on pin VDDA 0.5 3.6 V VBAT battery supply voltage on pin VBAT 0.5 3.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 9. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb +  P D  R th  j – a   (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 10. Static characteristics Table 11. Static characteristics Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Min Typ[1] Max Unit 2.2 - 3.6 V 2.2 - 3.6 V on pin VDDA 2.2 - 3.6 V on pins USB0_VDDA3V3_ DRIVER and USB0_VDDA3V3 3.0 3.3 3.6 V Conditions Supply pins VDD(IO) input/output supply voltage VDD(REG)(3V3) regulator supply voltage (3.3 V) VDDA(3V3) analog supply voltage (3.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol IBAT Parameter battery supply current Conditions VDD(REG)(3V3) = 3.3 V; VBAT = 3.6 V deep-sleep mode IBAT IDD(IO) IDDA battery supply current I/O supply current Analog supply current Min Typ[1] Max Unit - 1.5 - A - 1.5 - A - 1.5 - A - 3.0 - A 1.5 - A < 0.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Min Typ[1] Max Unit HIGH-level input voltage 0.7  VDD(IO) - 5.5 V VIL LOW-level input voltage 0.5 - 0.3  VDD(IO) V Vhys hysteresis voltage 0.1  VDD(IO) - - V VOH HIGH-level output voltage IOH = 6 mA VDD(IO)  0.4 - - V VOL LOW-level output voltage IOL = 6 mA - - 0.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Vhys hysteresis voltage Ipd pull-down current Min Typ[1] Max Unit 0.1  VDD(IO) - - V - 62 - A - 62 - A - 10 - A VI = VDD(IO); on-chip pull-down resistor disabled - 3 - nA VI = 5 V; Tamb = 25 °C - 0.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IOL LOW-level output current VOL = 0.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VOH HIGH-level output voltage IOH = 8 mA VDD(IO)  0.4 - - V VOL LOW-level output voltage IOL = 8 mA - - 0.4 V IOH HIGH-level output current VOH = VDD(IO)  0.4 V 8 - - mA IOL LOW-level output current VOL = 0.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 11. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VIC common-mode input voltage high-speed mode 50 200 500 mV full-speed/low-speed mode 800 - 2500 mV chirp mode 50 - 600 mV 100 400 1100 mV [17] - - 10 A [18] - - 5.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller [17] For USB operation 3.0 V  VDD((IO)  3.6 V. Guaranteed by design. [18] VDD(IO) present. [19] Includes external resistors of 33   1 % on D+ and D. 10.1 Power consumption aaa-013450 100 IDD(REG)(3V3) (mA) 204 MHz 80 180 MHz 60 120 MHz 40 60 MHz 20 12 MHz 0 2.2 2.4 2.6 2.8 3 3.2 3.4 VDD(REG)(3V3) (V) 3.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller aaa-013452 100 IDD(REG)(3V3) (mA) +105 °C +90 °C +25 °C 0 °C -40 °C 80 60 40 20 0 12 36 60 84 108 132 156 frequency (MHz) 180 Conditions: active mode entered executing code while (1){} from SRAM; M0 core in reset; VDD(REG)(3V3) = 3.3 V; system PLL enabled; IRC enabled; all peripherals disabled; all peripheral clocks disabled. Fig 13.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah410 1.6 IDD(REG)(3V3) (μA) (mA) 002aah412 300 IDD(REG)(3V3) (μA)(μA) 240 1.2 180 0.8 120 0.4 60 0 -40 0 40 80 temperature (°C) 0 -40 120 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V. 40 80 temperature (°C) 120 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V. Fig 15. Typical supply current versus temperature in Deep-sleep mode Fig 16.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah379 100 IBAT (μA) 80 60 40 20 0 -0.4 -0.2 0 0.2 0.4 VBAT - VDD(REG)(3V3) (V) 0.6 Conditions: VDD(REG)(3V3) = 3.0 V; VBAT = 2.6 V to 3.6 V; CCLK = 12 MHz. Remark: The recommended operating condition for the battery supply is VDD(REG)(3V3) > VBAT + 0.2 V. Fig 19. Typical battery supply current in Active mode 10.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 12. Peripheral power consumption Peripheral LPC435X_3X_2X_1X Product data sheet Branch clock IDD(REG)(3V3) in mA Branch clock frequency = 48 MHz Branch clock frequency = 96 MHz GPIO CLK_M4_GPIO 0.72 1.43 LCD CLK_M4_LCD 0.91 1.82 ETHERNET CLK_M4_ETHERNET 1.06 2.15 UART0 CLK_M4_UART0, CLK_APB0_UART0 0.24 0.43 UART1 CLK_M4_UART1, CLK_APB0_UART1 0.24 0.43 UART2 CLK_M4_UART2, CLK_APB2_UART2 0.26 0.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 10.3 Electrical pin characteristics 002aah368 3.6 VOH (V) 002aah359 3.6 VOH (V) -40 °C +25 °C +85 °C +105 °C 3.2 2.8 3.2 -40 °C +25 °C +85 °C +105 °C 2.8 2.4 2.4 2 2 0 16 32 48 64 80 IOH (mA) 96 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V. Product data sheet 6 12 18 24 30 IOH (mA) 36 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V. Fig 20.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah360 15 -40 °C +25 °C +85 °C +105 °C IOL (mA) 12 002aah361 25 -40 °C +25 °C +85 °C +105 °C IOL (mA) 20 9 15 6 10 3 5 0 0 0 0.1 0.2 0.3 0.4 0.5 VOL (V) 0.6 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; normal-drive; EHD = 0x0. 0 -40 °C +25 °C +85 °C +105 °C 32 0.2 0.3 0.4 0.5 VOL (V) 0.6 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; medium-drive; EHD = 0x1. 002aah362 40 IOL (mA) 0.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah364 3.6 VOH (V) 002aah367 3.6 VOH (V) -40 °C +25 °C +85 °C +105 °C 3.2 2.8 -40 °C +25 °C +85 °C +105 °C 3.2 2.8 2.4 2.4 2 2 0 4 8 12 16 20 IOH (mA) 24 0 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; normal-drive; EHD = 0x0. 16 24 32 40 IOH (mA) 48 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; medium-drive; EHD = 0x1. 002aah368 3.6 VOH (V) 8 002aah369 3.6 VOH (V) -40 °C +25 °C +85 °C +105 °C 3.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah422 20 IIpu pu (μA) 0 +105 °C C +25 °C C -40 °C C -20 -40 -60 -80 0 1 2 3 4 VI (V) 5 Conditions: VDD(IO) = 3.3 V. Simulated data over process and temperature. Fig 24. Pull-up current Ipu versus input voltage VI 002aah418 120 IIpd pd (μA) -40 °C C +25 °C C +105 °C C 90 60 30 0 0 1 2 3 4 VI (V) 5 Conditions: VDD(IO) = 3.3 V. Simulated data over process and temperature. Fig 25.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 10.4 BOD static characteristics Table 13. BOD static characteristics[1] Tamb = 25 C; simulated values for nominal processing. Symbol Parameter Conditions Vth threshold voltage interrupt level 0 Min Typ Max Unit assertion - 2.25 - V de-assertion - 2.33 - V assertion - 2.35 - V de-assertion - 2.43 - V assertion - 2.95 - V de-assertion - 3.03 - V assertion - 3.05 - V de-assertion - 3.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11. Dynamic characteristics 11.1 Flash/EEPROM memory Table 14. Flash characteristics Tamb = 40 C to +105 C, unless otherwise specified. VDD(REG)(3V3) = 2,2 V to 3.6 V for read operations; VDD(REG)(3V3) = 2.7 V to 3.6 V for erase/program operations.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.2 Wake-up times Table 16. Dynamic characteristic: Wake-up from Deep-sleep, Power-down, and Deep power-down modes Tamb = 40 C to +105 C Symbol Parameter twake Conditions Typ[1] Min Max Unit 3  Tcy(clk) 5  Tcy(clk) - ns from Deep-sleep and Power-down mode 12 51 - s from Deep power-down mode - 200 - μs after reset - 200 - μs [2] wake-up time from Sleep mode [1] Typical ratings are not guaranteed.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.4 Crystal oscillator Table 18. Dynamic characteristic: oscillator Tamb = 40 C to +105 C; VDD(IO) over specified ranges; 2.2 V  VDD(REG)(3V3)  3.6 V.[1] Symbol Parameter Conditions Low-frequency mode (1-20 tjit(per) Typ[2] Max Unit MHz)[5] period jitter time 5 MHz crystal High-frequency mode (20 - 25 tjit(per) Min [3][4] - 13.2 - ps 10 MHz crystal - 6.6 - ps 15 MHz crystal - 4.8 - ps - 4.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.7 I/O pins Table 21. Dynamic characteristic: I/O pins[1] Tamb = 40 C to +85 C; 2.7 V  VDD(IO)  3.6 V. Symbol Parameter Conditions Min Typ Max Unit Standard I/O pins - normal drive strength tr rise time pin configured as output; EHS = 1 [2][3] 1.0 - 2.5 ns tf fall time pin configured as output; EHS = 1 [2][3] 0.9 - 2.5 ns pin configured as output; EHS = 0 [2][3] 1.9 - 4.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.8 I2C-bus Table 22. Dynamic characteristic: I2C-bus pins Tamb = 40 C to +105 C; 2.2 V  VDD(REG)(3V3)  3.6 V.[1] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz [3][4][5][6] fall time tf Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz of both SDA and SCL signals - 300 ns Fast-mode 20 + 0.1  Cb 300 ns Fast-mode Plus - 120 ns Standard-mode 4.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller tf SDA tSU;DAT 70 % 30 % 70 % 30 % tHD;DAT tf 70 % 30 % SCL tVD;DAT tHIGH 70 % 30 % 70 % 30 % 70 % 30 % tLOW 1 / fSCL S 002aaf425 Fig 27. I2C-bus pins clock timing 11.9 I2S-bus interface Table 23. Dynamic characteristics: I2S-bus interface pins Tamb = 40 C to 105 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. Conditions and data refer to I2S0 and I2S1 pins. Simulated values.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Tcy(clk) tf tr I2Sx_TX_SCK tWH tWL I2Sx_TX_SDA tv(Q) I2Sx_TX_WS 002aag497 tv(Q) Fig 28. I2S-bus timing (transmit) Tcy(clk) tf tr I2Sx_RX_SCK tWH tWL I2Sx_RX_SDA tsu(D) th(D) I2Sx_RX_WS tsu(D) 002aag498 tsu(D) Fig 29. I2S-bus timing (receive) 11.10 USART interface Table 24. Dynamic characteristics: USART interface Tamb = 40 C to 105 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.11 SSP interface Table 25. Dynamic characteristics: SSP pins in SPI mode Tamb = 40 C to +85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. Simulated values. Symbol Tcy(clk) Parameter clock cycle time Conditions Min Typ Max Unit - 40 - ns when only transmitting - 20 - ns [1] full-duplex mode SSP master tDS data set-up time in SPI mode 13.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 25. Dynamic characteristics: SSP pins in SPI mode Tamb = 40 C to +85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. Simulated values. Symbol Parameter Conditions Min Typ Max Unit td delay time continuous transfer mode - 0.5 Tcy(clk) - - SPI mode; CPOL = 0; CPHA = 1 - n/a - - SPI mode; CPOL = 1; CPHA = 0 - 0.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.12 SPI interface Table 26. Dynamic characteristics: SPI Tamb = 40 C to +85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. Simulated values. Symbol Parameter Tcy(PCLK) PCLK cycle time Tcy(clk) clock cycle time Conditions Min Typ Max 5 [1] Unit ns 40 - - ns Master tDS data set-up time 7.2 - - ns tDH data hold time 0 - - ns tv(Q) data output valid time - - 3.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO th(Q) DATA VALID DATA VALID tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO DATA VALID CPHA = 1 th(Q) CPHA = 0 DATA VALID 002aae830 Fig 31. SSP in SPI mode and SPI slave timing LPC435X_3X_2X_1X Product data sheet All information provided in this document is subject to legal disclaimers. Rev.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.14 SPIFI Table 27. Dynamic characteristics: SPIFI Tamb = 40 C to 105 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. CL = 10 pF. Simulated values. Symbol Parameter Min Max Unit Tcy(clk) clock cycle time 9.6 - ns tDS data set-up time 3.4 - ns tDH data hold time 0 - ns tv(Q) data output valid time - 3.2 ns th(Q) data output hold time 0.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 28. Dynamic characteristics: SGPIO Tamb = 40 C to +85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. Simulated values.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.16 External memory interface Table 29. Dynamic characteristics: Static asynchronous external memory interface CL = 22 pF for EMC_Dn CL = 20 pF for all others; Tamb = 40 C to 105 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; values guaranteed by design. Timing parameters are given for single memory access cycles.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 29. Dynamic characteristics: Static asynchronous external memory interface …continued CL = 22 pF for EMC_Dn CL = 20 pF for all others; Tamb = 40 C to 105 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; values guaranteed by design. Timing parameters are given for single memory access cycles. In a normal read operation, the EMC changes the address while CS is asserted which results in multiple memory accesses.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller EMC_An tCSLAV tCSLAV tOEHANV tCSHEOW EMC_CSn tCSLOEL tOELOEH EMC_OE tCSLBLSL tCSHOEH tCSLBLSL EMC_BLSn tCSHBLSH tCSLWEL tWELWEH tWEHEOW EMC_WE tBLSHDNV tam tCSHEOR th(D) tCSLSOR tCSLDV tWEHDNV EMC_Dn SOR EOR EOW 002aag700 Fig 35. External static memory read/write access (PB = 1) LPC435X_3X_2X_1X Product data sheet All information provided in this document is subject to legal disclaimers. Rev.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 30. Dynamic characteristics: Dynamic external memory interface Simulated data over temperature and process range; CL = 10 pF for EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE, EMC_An; CL = 9 pF for EMC_Dn; CL = 5 pF for EMC_DQMOUTn, EMC_CLKn, EMC_CKEOUTn; Tamb = 40 C to 105 C; 2.2 V  VDD(REG)(3V3)  3.6 V; VDD(IO) =3.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller EMC_CLKn delay > 0 EMC_CLKn delay td; programmable CLKn_DELAY Tcy(clk) EMC_CLKn delay = 0 td(xV) - td EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE, EMC_CKEOUTn, EMC_A[22:0], EMC_DQMOUTn td(xV) th(x) - td th(x) td(QV) - td td(QV) th(Q) - td th(Q) EMC_D[31:0] write tsu(D) th(D) EMC_D[31:0] read; delay > 0 tsu(D) th(D) EMC_D[31:0] read; delay = 0 002aag703 For the programmable EMC_CLK[3:0] clock delays CLKn_DELAY, see Table 31.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.17 USB interface Table 32. Dynamic characteristics: USB0 and USB1 pins (full-speed) CL = 50 pF; Rpu = 1.5 k on D+ to VDD(IO), unless otherwise specified; 3.0 V  VDD(IO)  3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 % to 90 % 8.5 - 13.8 ns tf fall time 10 % to 90 % 7.7 - 13.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Static characteristics: USB0 PHY pins[1] Table 33. Symbol Parameter Conditions Min Typ Max Unit - 68 - mW - 18 - mA High-speed mode Pcons [2] power consumption IDDA(3V3) analog supply current (3.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 34. Dynamic characteristics: Ethernet Tamb = 40 C to 105 C, 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. Values guaranteed by design.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.19 SD/MMC Table 35. Dynamic characteristics: SD/MMC Tamb = 40 C to 85 C, 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V, CL = 20 pF. Simulated values. SAMPLE_DELAY = 0x8, DRV_DELAY = 0xF in the SDDELAY register (see the LPC43xx user manual UM10430).
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 12. ADC/DAC electrical characteristics Table 37. ADC characteristics VDDA(3V3) over specified ranges; Tamb = 40 C to +105 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VIA analog input voltage 0 - VDDA(3V3) V Cia analog input capacitance - - 2 pF ED differential linearity error - 0.8 - LSB - 1.0 - LSB - 0.8 - LSB - 1.5 - LSB - 0.15 - LSB - 0.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = VDDA(3V3) − VSSA 1024 002aaf959 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Rvsi LPC43xx 2 kΩ (analog pin) 2.2 kΩ (multiplexed pin) ADC0_n/ADC1_n Rs ADC COMPARATOR Cia = 2 pF VEXT VSS 002aah084 Rs < 1/((7  fclk(ADC)  Cia)  2 k Fig 41. ADC interface to pins Table 38. DAC characteristics VDDA(3V3) over specified ranges; Tamb = 40 C to +105 C; unless otherwise specified Symbol Parameter Conditions ED differential linearity error 2.7 V  VDDA(3V3)  3.6 V [1] 2.2 V  VDDA(3V3) < 2.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 13. Application information 13.1 LCD panel signal usage Table 39.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 40.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 41.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 42. Recommended values for CX1/X2 in oscillation mode (crystal and external components parameters) low frequency mode Fundamental oscillation frequency Maximum crystal series resistance RS External load capacitors CX1, CX2 12 MHz < 160  18 pF, 18 pF < 160  39 pF, 39 pF 16 MHz < 120  18 pF, 18 pF < 80  33 pF, 33 pF < 100  18 pF, 18 pF < 80  33 pF, 33 pF 20 MHz Table 43.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 13.3 RTC oscillator In the RTC oscillator circuit, only the crystal (XTAL) and the capacitances CRTCX1 and CRTCX2 need to be connected externally. Typical capacitance values for CRTCX1 and CRTCX2 are CRTCX1/2 = 20 (typical)  4 pF. An external clock can be connected to RTCX1 if RTCX2 is left open. The recommended amplitude of the clock signal is Vi(RMS) = 100 mV to 200 mV with a coupling capacitance of 5 pF to 10 pF.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller VDDIO ESD enable output driver data output from core PIN slew rate bit EHS input buffer enable bit EZI data input to core glitch filter filter select bit ZIF pull-up enable bit EPUN ESD pull-down enable bit EPD analog I/O VSSIO 002aah028 The glitch filter rejects pulses of typical 12 ns width. Fig 45. Standard I/O pin configuration with analog input 13.5.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller On the LPC435x/3x/2x/1x, USBn_VBUS pins are 5 V tolerant only when VDDIO is applied and at operating voltage level. Therefore, if the USBn_VBUS function is connected to the USB connector and the device is self-powered, the USBn_VBUS pins must be protected for situations when VDDIO = 0 V. If VDDIO is always at operating level while VBUS = 5 V, the USBn_VBUS pin can be connected directly to the VBUS pin on the USB connector.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller LPC43xx VDDIO REGULATOR USBn_VBUS VBUS USB-B connector USB aaa-013459 Fig 48. USB interface on a bus-powered device Remark: If the VBUS function of the USB1 interface is not connected, configure the pin function for GPIO using the function control bits in the SYSCON block. VDDIO R1 LPC43xx T2 T1 R2 R3 USBn_VBUS VBUS USB-B connector USB aaa-013460 Fig 49.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 14.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller LQFP208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459-1 c y X A 105 156 157 104 ZE e E HE (A 3) A A2 A1 wM θ Lp bp L detail X pin 1 index 208 53 1 52 v M A ZD wM bp e D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 28.1 27.9 28.1 27.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm B D SOT926-1 A ball A1 index area A2 E A A1 detail X e1 e ∅v ∅w b 1/2 e C M M C A B C y y1 C K J e H G F e2 E D 1/2 e C B A ball A1 index area 1 2 3 4 5 6 7 8 9 10 X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 A2 b D E e e1 e2 v w y y1 mm 1.2 0.4 0.3 0.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1 c y X A 73 72 108 109 ZE e E HE A A2 (A 3) A1 θ wM Lp bp L pin 1 index detail X 37 144 1 36 v M A ZD wM bp e D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 20.1 19.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 15. Soldering Footprint information for reflow soldering of LBGA256 package SOT740-2 Hx P P Hy see detail X Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste SL SP occupied area SR solder resist detail X DIMENSIONS in mm P SL SP SR 1.00 0.450 0.450 0.600 Hx Hy 17.500 17.500 sot740-2_fr Fig 54.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Footprint information for reflow soldering of LQFP208 package SOT459-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 31.300 31.300 28.300 28.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 28.500 28.500 31.550 31.550 sot459-1_fr Fig 55.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Footprint information for reflow soldering of LQFP144 package SOT486-1 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 0.500 P2 Ax Ay Bx By 0.560 23.300 23.300 20.300 20.300 C D1 D2 1.500 0.280 0.400 Gx Gy Hx Hy 20.500 20.500 23.550 23.550 sot486-1_fr Fig 56.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Footprint information for reflow soldering of TFBGA100 package SOT926-1 Hx P P Hy see detail X Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste SL SP occupied area SR solder resist detail X DIMENSIONS in mm P SL SP SR Hx Hy 0.80 0.330 0.400 0.480 9.400 9.400 sot926-1_fr Fig 57.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 16. Abbreviations Table 44.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 17. References LPC435X_3X_2X_1X Product data sheet [1] LPC43xx User manual UM10430: http://www.nxp.com/documents/user_manual/UM10503.pdf [2] LPC43xx Errata sheet: http://www.nxp.com/documents/errata_sheet/ES_LPC43XX.pdf All information provided in this document is subject to legal disclaimers. Rev. 4 — 19 August 2014 © NXP Semiconductors N.V. 2014. All rights reserved.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 18. Revision history Table 45. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC435X_3X_2X_1X v.4 20140819 - Modifications: • • • • Product data sheet LPC435X_3X_2X_1X v.3 Parameter tret (retention time) for EEPROM updated in Table 15. SGPIO and SPI location corrected in Figure 1. SGPIO-to-DMA connection updated in Figure 6.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 45. Revision history …continued Document ID Modifications: LPC435X_3X_2X_1X v.3 Modifications: LPC4357_53_37_33 v.2.1 Modifications: LPC435X_3X_2X_1X Product data sheet Release date Data sheet status • • Change notice Supersedes SD/MMC timing data updated. See Table 35 “Dynamic characteristics: SD/MMC”. IEEE standard 802.3 compliance added to Section 11.18.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 45. Revision history …continued Document ID Release date Data sheet status Change notice Supersedes LPC4357_53_37_33 v.2 20120711 - Modifications: LPC4357_53 v.1 LPC435X_3X_2X_1X Product data sheet • • • Preliminary data sheet LPC4357_53 v.1 Data sheet status changed to preliminary. Parts LPC4337 and LPC4333 added.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 5 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 6 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
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LPC435x/3x/2x/1x NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.23.5 7.23.6 7.23.7 7.23.8 7.23.9 7.23.10 7.23.11 7.24 8 9 10 10.1 10.2 10.3 10.4 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 11.10 11.11 11.12 11.13 11.14 11.15 11.16 11.17 11.18 11.19 11.20 12 13 13.1 13.2 13.3 13.4 13.5 13.5.1 13.5.2 14 15 16 PLL0USB (for USB0) . . . . . . . . . . . . . . . . . . . 84 PLL0AUDIO (for audio) . . . . . . . . . . . . . . . . . 84 System PLL1 . . . . . . . . . . . . . . . . . . . . . . . . .