Datasheet

LPC435X_3X_2X_1X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4 — 19 August 2014 152 of 158
NXP Semiconductors
LPC435x/3x/2x/1x
32-bit ARM Cortex-M4/M0 microcontroller
18. Revision history
Table 45. Revision history
Document ID Release date Data sheet status Change notice Supersedes
LPC435X_3X_2X_1X v.4 20140819 Product data sheet - LPC435X_3X_2X_1X v.3
Modifications:
• Parameter t
ret
(retention time) for EEPROM updated in Table 15.
• SGPIO and SPI location corrected in Figure 1.
• SGPIO-to-DMA connection updated in Figure 6.
• Parameter V
DDA(3V3)
added for pins USB0_VDDA3V3_DRIVER and
USB0_VDDA3V3 in Table 11.
• Parameter name I
DD(ADC)
changed to I
DDA
in Table 11.
• Minimum wake-up time from sleep mode added in Ta ble 16 .
• Data for I
DD(IO)
added in Table 11.
• Corrected max voltage on pins USB0_DP, USB0_DM, USB0_VBUS, USB1_DP, and
USB1_DM in Tab le 7 and Table 11 to be consistent with USB specifications.
• SPI and SGPIO peripheral power consumption added in Table 12.
• SPI timing characteristics added. See Section 11.12.
• SGPIO timing characteristics added. See Section 11.15.
• Data sheet status changed to Product data sheet.
• Conditions RPHASE1 and RPHASE2 corrected in Table 15 “EEPROM
characteristics”. RPHASE1: t
wait
> 70 ns. RPHASE2: t
wait
> 35 ns.
• I
DD(REG)(3V3)
updated in Table 11 “Static characteristics” for the following conditions:
– Active mode: CCLK = 12 MHz; I
DD(REG)(3V3)
changed from 9.3 mA to 10 mA.
– Active mode: CCLK = 60 MHz; I
DD(REG)(3V3)
changed from 26 mA to 28 mA.
– Active mode: CCLK = 120 MHz; I
DD(REG)(3V3)
changed from 46 mA to 51 mA.
– Active mode: CCLK = 180 MHz; I
DD(REG)(3V3)
changed from 66 mA to 74 mA.
– Active mode: CCLK = 204 MHz; I
DD(REG)(3V3)
changed from 75 mA to 83 mA.
– Sleep mode: CCLK = 12 MHz; I
DD(REG)(3V3)
changed from 6.2 mA to 8.8 mA.
• Power consumption data in Figure 11 to Figure 14 updated.
• IRC specifications corrected in Table 19 “Dynamic characteristic: IRC oscillator”.
Accuracy changed to +/- 3 % over the entire temperature range.
• SPIFI timing diagram corrected and specified for mode 0. See Ta ble 27.
• Table 21 “Dynamic characteristic: I/O pins
[1]
” added.
• Parameter C
I
corrected for high-drive pins (changed from 2 pF to 5.2 pF). See
Table 11
.
• Internal pull-up resistor configuration added for RESET, WAKEUPn, and ALARM
pins. See Table 3.
• Description of DEBUG pin updated.
• Input range for PLL1 corrected: 1 MHz to 25 MHz. See Section 7.23.7 “System PLL1”.
• Signal polarity of EMC_CKEOUT and EMC_DQMOUT corrected. Both signals are
active HIGH.
• SPIFI output timing parameters in Ta ble 27 corrected to apply to Mode 0:
– t
v(Q)
changed to 3.2 ns.
– t
h(Q)
changed to 0.2 ns,