Datasheet

Product data sheet Rev. 4 — 19 August 2014 85 of 158

NXP Semiconductors

LPC435x/3x/2x/1x

32-bit ARM Cortex-M4/M0 microcontroller

7.23.7 System PLL1

The PLL1 accepts an input clock frequency from an external oscillator in the range of

1 MHz to 25 MHz. The input frequency is multiplied up to a high frequency with a Current

Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32. The CCO

operates in the range of 156 MHz to 320 MHz. This range is possible through an

additional divider in the loop to keep the CCO within its frequency range while the PLL is

providing the desired output frequency. The output divider can be set to divide by 2, 4, 8,

or 16 to produce the output clock. Since the minimum output divider value is 2, it is

insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed

following a chip reset. After reset, software can enable the PLL. The program must

configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a

clock source. The PLL settling time is 100 s.

7.23.8 Reset Generation Unit (RGU)

The RGU allows generation of independent reset signals for individual blocks and

peripherals on the LPC435x/3x/2x/1x.

7.23.9 Power Management Controller (PMC)

The PMC controls the power to the cores, peripherals, and memories.

The LPC435x/3x/2x/1x support the following power modes in order from highest to lowest

power consumption:

1. Active mode

2. Sleep mode

3. Power-down modes:

a. Deep-sleep mode

b. Power-down mode

c. Deep power-down mode

Active mode and sleep mode apply to the state of the core. In a dual-core system, either

core can be in active or sleep mode independently of the other core.

If the core is in Active mode, it is fully operational and can access peripherals and

memories as configured by software. If the core is in Sleep mode, it receives no clocks,

but peripherals and memories remain running.

Either core can enter sleep mode from active mode independently of the other core and

while the other core remains in active mode or is in sleep mode.

Power-down modes apply to the entire system. In the Power-down modes, both cores and

all peripherals except for peripherals in the always-on power domain are shut down.

Memories can remain powered for retaining memory contents as defined by the individual

power-down mode.

Either core in active mode can put the part into one of the three power down modes if the

core is enabled to do so. If both cores are enabled for putting the system into power-down,

then the system enters power-down only once both cores have received a WFI or WFE

instruction.