Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LBGA 256 (17x17) 32-Bit Tri-Core 204 MHz I/O number 164

1. General description

The LPC4370 are ARM Cortex-M4 based microcontrollers for embedded applications

which include an ARM Cortex-M0 coprocessor and an ARM Cortex-M0 subsystem for

managing peripherals, 282 kB of SRAM, advanced configurable peripherals such as the

State Configurable Timer (SCT) and the Serial General Purpose I/O (SGPIO) interface,

two High-speed USB controllers, Ethernet, LCD, an external memory controller, and

multiple digital and analog peripherals including a high-speed 12-bit ADC. The LPC4370

operate at CPU frequencies of up to 204 MHz.

The ARM Cortex-M4 is a next generation 32-bit core that offers system enhancements

such as low power consumption, enhanced debug features, and a high level of support

block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a

Harvard architecture with separate local instruction and data buses as well as a third bus

for peripherals, and includes an internal prefetch unit that supports speculative branching.

The ARM Cortex-M4 supports single-cycle digital signal processing and SIMD

instructions. A hardware floating-point processor is integrated in the core.

The LPC4370 include an application ARM Cortex-M0 coprocessor and a second ARM

Cortex-M0 subsystem for managing the SGPIO and SPI peripherals. The ARM Cortex-M0

core is an energy-efficient and easy-to-use 32-bit core which is code- and tool-compatible

with the Cortex-M4 core. Both Cortex-M0 cores offer up to 204 MHz performance with a

simple instruction set and reduced code size.

2. Features and benefits

 Main Cortex-M4 processor

 ARM Cortex-M4 processor, running at frequencies of up to 204 MHz.

 ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions.

 ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).

 Hardware floating-point unit.

 Non-maskable Interrupt (NMI) input.

 JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch

points.

 Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.

 System tick timer.

 Cortex-M0 coprocessor

 ARM Cortex-M0 coprocessor capable of off-loading the main ARM Cortex-M4

processor.

 Running at frequencies of up to 204 MHz.

LPC4370

32-bit ARM Cortex-M4 + 2 x M0 MCU; 282 kB SRAM; Ethernet;

two HS USBs; 80 Msps 12-bit ADC; configurable peripherals

Rev. 2 — 21 October 2013 Product data sheet

Summary of content (150 pages)

PAGE 1
LPC4370 32-bit ARM Cortex-M4 + 2 x M0 MCU; 282 kB SRAM; Ethernet; two HS USBs; 80 Msps 12-bit ADC; configurable peripherals Rev. 2 — 21 October 2013 Product data sheet 1.
PAGE 2
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller      LPC4370 Product data sheet  JTAG and built-in NVIC. Cortex-M0 subsystem  ARM Cortex-M0 processor controlling the SPI and SGPIO peripherals residing on a separate AHB multilayer matrix with direct access to 2 kB + 16 kB of SRAM.  Running at frequencies of up to 204 MHz.  Connected via a core-to-core bridge to the main AHB multilayer matrix and the main ARM Cortex-M4 processor.  JTAG and built-in NVIC.
PAGE 3
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller     LPC4370 Product data sheet  LCD controller with DMA support and a programmable display resolution of up to 1024 H  768 V. Supports monochrome and color STN panels and TFT color panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel mapping.  Secure Digital Input Output (SD/MMC) card interface.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller  Processor wake-up from Sleep mode via wake-up interrupts from various peripherals.  Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain.  Brownout detect with four separate thresholds for interrupt and forced reset.  Power-On Reset (POR).  Available as LBGA256 and TFBGA100 packages. 3.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC4370FET256 LBGA256 Plastic low profile ball grid array package; 256 balls; body 17  17  1 mm SOT740-2 LPC4370FET100 TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9  9  0.7 mm SOT926-1 4.1 Ordering options Table 2.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 5.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 6. Pinning information 6.1 Pinning LPC4370FET256 ball A1 index area 2 1 4 3 6 5 8 7 10 9 12 11 14 13 ball A1 index area 16 LPC4370FET100 1 15 A 2 3 4 5 6 7 8 A B C B E C D F D G E H J F L G K M H N J P R K T 002aag608 002aag607 Transparent top view Transparent top view Fig 2. 9 10 Pin configuration LBGA256 package Fig 3. Pin configuration TFBGA100 package 6.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Type Description [2] TFBGA100 LBGA256 Symbol Reset state Table 3. Pin description LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. Multiplexed digital pins P0_0 P0_1 L3 M2 G2 G1 [3] [3] I; PU I/O GPIO0[0] — General purpose digital input/output pin. I/O SSP1_MISO — Master In Slave Out for SSP1. I ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface).
PAGE 9
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P1_3 P1_4 P1_5 K1 P5 T3 R5 LPC4370 Product data sheet J1 J2 J4 [3] [3] [3] [3] Type R3 Description [2] TFBGA100 P1_2 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO0[9] — General purpose digital input/output pin. Boot pin (see Table 5). O CTOUT_6 — SCT output 6. Match output 2 of timer 1.
PAGE 10
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P1_7 K4 T5 G4 [3] [3] Type T4 Description [2] TFBGA100 P1_6 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO1[9] — General purpose digital input/output pin. I CTIN_5 — SCT input 5. Capture input 2 of timer 2. - R — Function reserved. O EMC_WE — LOW active Write Enable signal. - R — Function reserved.
PAGE 11
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P1_11 P1_12 P1_13 H6 T9 R9 R10 LPC4370 Product data sheet J7 K7 H8 [3] [3] [3] [3] Type R8 Description [2] TFBGA100 P1_10 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO1[3] — General purpose digital input/output pin. I U1_RI — Ring Indicator input for UART1. O CTOUT_14 — SCT output 14.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P1_15 P1_16 P1_17 J8 T12 M7 M8 LPC4370 Product data sheet K8 H9 H10 [3] [3] [3] [4] Type R11 Description [2] TFBGA100 P1_14 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO1[7] — General purpose digital input/output pin. I U1_RXD — Receiver input for UART1. - R — Function reserved.
PAGE 13
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P1_19 P1_20 J10 M11 M10 K9 K10 [3] [3] [3] Type N12 Description [2] TFBGA100 P1_18 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O I/O U2_DIR — RS-485/EIA-485 output enable/direction control for USART2. - R — Function reserved. O ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface).
PAGE 14
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P2_2 P2_3 P2_4 G7 M15 J12 K11 LPC4370 Product data sheet F5 D8 D9 [3] [3] [4] [4] Type N15 Description [2] TFBGA100 P2_1 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O SGPIO5 — General purpose digital input/output pin. I U0_RXD — Receiver input for USART0.
PAGE 15
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller D10 [4] Type K14 Description [2] TFBGA100 P2_5 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O SGPIO14 — General purpose digital input/output pin. I CTIN_2 — SCT input 2. Capture input 2 of timer 0. I USB1_VBUS — Monitors the presence of USB1 bus power. Note: This signal must be HIGH for USB reset to occur.
PAGE 16
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P2_10 P2_11 P2_12 B10 G16 F16 E15 LPC4370 Product data sheet E8 A9 B9 [3] [3] [3] [3] Type H16 Description [2] TFBGA100 P2_9 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO1[10] — General purpose digital input/output pin. Boot pin (see Table 5). O CTOUT_3 — SCT output 3. Match output 3 of timer 0.
PAGE 17
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P3_0 A10 F13 A8 [3] [3] Type C16 Description [2] TFBGA100 P2_13 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O I CTIN_4 — SCT input 4. Capture input 2 of timer 1. - R — Function reserved. I/O EMC_A4 — External memory address line 4. - R — Function reserved. - R — Function reserved.
PAGE 18
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P3_4 P3_5 P3_6 A7 A15 C12 B13 LPC4370 Product data sheet B8 B7 C7 [5] [3] [3] [3] Type B14 Description [2] TFBGA100 P3_3 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. I/O SPI_SCK — Serial clock for SPI. I/O SSP0_SCK — Serial clock for SSP0.
PAGE 19
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P3_8 P4_0 P4_1 D7 C10 D5 A1 E7 - - [3] [3] [3] [6] [13] LPC4370 Product data sheet Type C11 Description [2] TFBGA100 P3_7 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. I/O SPI_MOSI — Master Out Slave In for SPI. I/O SSP0_MISO — Master In Slave Out for SSP0.
PAGE 20
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P4_3 - C2 - [3] [6] [13] P4_4 P4_5 B1 D2 LPC4370 Product data sheet - - [6] [3] Type D3 Description [2] TFBGA100 P4_2 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO2[2] — General purpose digital input/output pin. O CTOUT_0 — SCT output 0. Match output 0 of timer 0. O LCD_VD3 — LCD data.
PAGE 21
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P4_7 P4_8 - H4 E2 - - [3] [3] [3] Type C1 Description [2] TFBGA100 P4_6 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O O; PU O CTOUT_4 — SCT output 4. Match output 0 of timer 1. O LCD_ENAB/LCDM — STN AC bias drive or TFT data enable input. - R — Function reserved. - R — Function reserved.
PAGE 22
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P5_0 P5_1 P5_2 - N3 P3 R4 LPC4370 Product data sheet - - - [3] [3] [3] [3] Type M3 Description [2] TFBGA100 P4_10 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. I CTIN_2 — SCT input 2. Capture input 2 of timer 0. O LCD_VD10 — LCD data. - R — Function reserved.
PAGE 23
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P5_4 P5_5 P5_6 - P9 P10 T13 LPC4370 Product data sheet - - - [3] [3] [3] [3] Type T8 Description [2] TFBGA100 P5_3 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO2[12] — General purpose digital input/output pin. I MCI0 — Motor control PWM channel 0, input.
PAGE 24
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P6_0 P6_1 P6_2 - M12 R15 L13 LPC4370 Product data sheet H7 G5 J9 [3] [3] [3] [3] Type R12 Description [2] TFBGA100 P5_7 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO2[7] — General purpose digital input/output pin. O MCOA2 — Motor control PWM channel 2, output A.
PAGE 25
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P6_4 P6_5 P6_6 - R16 P16 L14 LPC4370 Product data sheet F6 F9 - [3] [3] [3] [3] Type P15 Description [2] TFBGA100 P6_3 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO3[2] — General purpose digital input/output pin.
PAGE 26
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P6_8 P6_9 P6_10 - H13 J15 H15 LPC4370 Product data sheet - F8 - [3] [3] [3] [3] Type J13 Description [2] TFBGA100 P6_7 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. I/O EMC_A15 — External memory address line 15. I/O SGPIO6 — General purpose digital input/output pin.
PAGE 27
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P6_12 P7_0 P7_1 C9 G15 B16 C14 LPC4370 Product data sheet - - - [3] [3] [3] [3] Type H12 Description [2] TFBGA100 P6_11 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO3[7] — General purpose digital input/output pin. - R — Function reserved. - R — Function reserved.
PAGE 28
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P7_3 P7_4 P7_5 - C13 C8 A7 LPC4370 Product data sheet - - - [3] [3] [6] [6] Type A16 Description [2] TFBGA100 P7_2 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO3[10] — General purpose digital input/output pin. I CTIN_4 — SCT input 4. Capture input 2 of timer 1.
PAGE 29
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P7_7 - B6 - [3] [6] [13] P8_0 E5 - [4] [13] P8_1 H5 LPC4370 Product data sheet - [4] Type C7 Description [2] TFBGA100 P7_6 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO3[14] — General purpose digital input/output pin. O CTOUT_11 — SCT output 1. Match output 3 of timer 2.
PAGE 30
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P8_3 P8_4 P8_5 - J3 J2 J1 LPC4370 Product data sheet - - - [4] [3] [3] [3] Type K4 Description [2] TFBGA100 P8_2 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO4[2] — General purpose digital input/output pin. O USB0_IND0 — USB0 port indicator LED control output 0. - R — Function reserved.
PAGE 31
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller - [3] Type K3 Description [2] TFBGA100 P8_6 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O I USB1_ULPI_NXT — ULPI link NXT signal. Data flow control signal from the PHY. - R — Function reserved. O LCD_VD5 — LCD data. O LCD_LP — Line synchronization pulse (STN). Horizontal synchronization pulse (TFT).
PAGE 32
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller - [3] Type N6 Description [2] TFBGA100 P9_1 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O O MCOA2 — Motor control PWM channel 2, output A. - R — Function reserved. - R — Function reserved. I/O I2S0_TX_WS — Transmit Word Select. It is driven by the master and received by the slave.
PAGE 33
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller P9_6 - L11 - [3] [3] Type M9 Description [2] TFBGA100 P9_5 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU O MCOA1 — Motor control PWM channel 1, output A. O USB1_VBUS_EN — USB1 VBUS power enable. - R — Function reserved. I/O GPIO5[18] — General purpose digital input/output pin.
PAGE 34
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PA_3 PA_4 PB_0 - H11 G13 B15 LPC4370 Product data sheet - - - [4] [4] [3] [3] Type K15 Description [2] TFBGA100 PA_2 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O GPIO4[9] — General purpose digital input/output pin. I QEI_PHB — Quadrature Encoder Interface PHB input. - R — Function reserved.
PAGE 35
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PB_2 PB_3 PB_4 - B12 A13 B11 LPC4370 Product data sheet - - - [3] [3] [3] [3] Type A14 Description [2] TFBGA100 PB_1 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. I USB1_ULPI_DIR — ULPI link DIR signal. Controls the ULP data line direction. O LCD_VD22 — LCD data.
PAGE 36
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PB_6 - A6 - [3] [6] [13] PC_0 D4 - [6] [13] PC_1 E4 LPC4370 Product data sheet - [3] Type A12 Description [2] TFBGA100 PB_5 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. I/O USB1_ULPI_D4 — ULPI link bidirectional data line 4. O LCD_VD14 — LCD data. - R — Function reserved.
PAGE 37
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PC_3 PC_4 - F5 F4 - - [3] [6] [3] Type F6 Description [2] TFBGA100 PC_2 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I/O USB1_ULPI_D6 — ULPI link bidirectional data line 6. - R — Function reserved. I U1_CTS — Clear to Send input for UART 1. O ENET_TXD2 — Ethernet transmit data 2 (MII interface).
PAGE 38
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PC_7 PC_8 PC_9 - G5 N4 K2 LPC4370 Product data sheet - - - [3] [3] [3] [3] Type H6 Description [2] TFBGA100 PC_6 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. I/O USB1_ULPI_D2 — ULPI link bidirectional data line 2. - R — Function reserved.
PAGE 39
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PC_11 - L5 - [3] [3] Type M5 Description [2] TFBGA100 PC_10 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU O USB1_ULPI_STP — ULPI link STP signal. Asserted to end or interrupt transfers to the PHY. I U1_DSR — Data Set Ready input for UART 1. - R — Function reserved.
PAGE 40
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PD_0 PD_1 PD_2 - N2 P1 R1 LPC4370 Product data sheet - - - [3] [3] [3] [3] Type N1 Description [2] TFBGA100 PC_14 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. - R — Function reserved. I U1_RXD — Receiver input for UART 1. - R — Function reserved.
PAGE 41
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PD_4 PD_5 PD_6 - T2 P6 R6 LPC4370 Product data sheet - - - [3] [3] [3] [3] Type P4 Description [2] TFBGA100 PD_3 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. O CTOUT_6 — SCT output 7. Match output 2 of timer 1. I/O EMC_D17 — External memory data line 17.
PAGE 42
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PD_8 PD_9 PD_10 - P8 T11 P11 LPC4370 Product data sheet - - - [3] [3] [3] [3] Type T6 Description [2] TFBGA100 PD_7 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. I CTIN_5 — SCT input 5. Capture input 2 of timer 2. I/O EMC_D21 — External memory data line 21.
PAGE 43
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PD_12 PD_13 PD_14 - N11 T14 R13 LPC4370 Product data sheet - - - [3] [3] [3] [3] Type N9 Description [2] TFBGA100 PD_11 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. - R — Function reserved. O EMC_CS3 — LOW active Chip Select 3 signal. - R — Function reserved.
PAGE 44
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PD_16 PE_0 PE_1 - R14 P14 N14 LPC4370 Product data sheet - - - [3] [3] [3] [3] Type T15 Description [2] TFBGA100 PD_15 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. - R — Function reserved. I/O EMC_A17 — External memory address line 17. - R — Function reserved.
PAGE 45
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PE_3 PE_4 PE_5 - K12 K13 N16 LPC4370 Product data sheet - - - [3] [3] [3] [3] Type M14 Description [2] TFBGA100 PE_2 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU I ADCTRIG0 — ADC trigger input 0. I CAN0_RD — CAN receiver input. - R — Function reserved. I/O EMC_A20 — External memory address line 20.
PAGE 46
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PE_7 PE_8 PE_9 - F15 F14 E16 LPC4370 Product data sheet - - - [3] [3] [3] [3] Type M16 Description [2] TFBGA100 PE_6 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. O CTOUT_2 — SCT output 2. Match output 2 of timer 0. I U1_RI — Ring Indicator input for UART 1.
PAGE 47
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PE_11 PE_12 PE_13 - D16 D15 G14 LPC4370 Product data sheet - - - [3] [3] [3] [3] Type E14 Description [2] TFBGA100 PE_10 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. I CTIN_3 — SCT input 3. Capture input 1 of timer 1. O U1_DTR — Data Terminal Ready output for UART 1.
PAGE 48
LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PE_15 PF_0 PF_1 - E13 D12 E11 LPC4370 Product data sheet - - - [3] [3] [3] [3] Type C15 Description [2] TFBGA100 PE_14 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. - R — Function reserved. - R — Function reserved. O EMC_DYCS3 — SDRAM chip select 3.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PF_3 PF_4 PF_5 - E10 D10 E9 LPC4370 Product data sheet - H4 - [3] [3] [3] [6] Type D11 Description [2] TFBGA100 PF_2 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. O U3_TXD — Transmitter output for USART3. I/O SSP0_MISO — Master In Slave Out for SSP0. - R — Function reserved.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller PF_7 PF_8 - B7 E6 - - [6] [6] [6] [13] LPC4370 Product data sheet Type E7 Description [2] TFBGA100 PF_6 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. I/O U3_DIR — RS-485/EIA-485 output enable/direction control for USART3. I/O SSP1_MISO — Master In Slave Out for SSP1.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller - [6] [13] PF_10 A3 - [6] [13] PF_11 A2 - [6] [13] LPC4370 Product data sheet Type D6 Description [2] TFBGA100 PF_9 LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I; PU - R — Function reserved. I/O U0_DIR — RS-485/EIA-485 output enable/direction control for USART0. O CTOUT_1 — SCT output 1.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller K3 Type TFBGA100 N5 Description [2] LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. Clock pins CLK0 CLK1 CLK2 CLK3 T10 D14 P12 - K6 - [5] [5] [5] [5] O; PU O; PU O; PU O; PU O EMC_CLK0 — SDRAM clock 0. O CLKOUT — Clock output pin. - R — Function reserved. - R — Function reserved.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller H2 [3] I; F Type J5 [2] TFBGA100 TCK/SWDCLK Description LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. I Test Clock for JTAG interface (default) or Serial Wire (SW) clock. TRST M4 B4 [3] I; PU I Test Reset for JTAG interface.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller E3 A2 [9] I; IA I 12-bit high-speed ADC input channel 0. ADCHS_1 C3 A1 [9] I; IA I 12-bit high-speed ADC input channel 1. I; IA I 12-bit high-speed ADC input channel 2. Type ADCHS_0 [2] TFBGA100 Description LBGA256 Symbol Reset state Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller VDDIO D7, F10, E12, K5 F7, F8, G10, H10, J6, J7, K7, L9, L10, N7, N13 VDD - - VSS G9, H7, J10, J11, K8 VSSIO VSSA Type Description [2] Reset state LBGA256 Symbol TFBGA100 Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2. - - I/O power supply.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller [6] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output (5 V tolerant if VDD(IO) present; if VDD(IO) not present, do not exceed 3.3 V). When configured as a ADC input or DAC output, the pin is not 5 V tolerant and the digital section of the pad must be disabled by setting the pin to an input function and disabling the pull-up resistor through the pin’s SFSP register.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7. Functional description 7.1 Architectural overview The ARM Cortex-M4 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus. The I-code and D-code core buses allow for concurrent code and data accesses from different slave ports.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller One of the two SRAM blocks connected to the subsystem AHB matrix is typically used for code running on the M0 subsystem and the other SRAM block for data. This allows other bus masters to access the data SRAM without interrupting the M0 processor instruction fetches and thereby stalling the M0 subsystem. The M0 subsystem matrix runs at an asynchronous speed from the main matrix. This allows to operate the SGPIO at any desired frequency.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Each ARM Cortex-M0 coprocessor has its own NVIC with 32 vectored interrupts. Most peripheral interrupts are shared between the two Cortex-M0cores and the Cortex-M4 NVICs. 7.6.1 Features • ARM Cortex-M4 NVIC: – Controls system exceptions and peripheral interrupts. – Up to 53 vectored interrupts. – Eight programmable interrupt priority levels with hardware priority level masking. – Relocatable vector table. – Non-Maskable Interrupt (NMI).
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.9 Global Input Multiplexer Array (GIMA) The GIMA allows to route signals to event-driven peripheral targets like the SCT, timers, event router, or the ADCs. 7.9.1 Features • • • • • Single selection of a source. Signal inversion. Can capture a pulse if the input event source is faster than the target clock. Synchronization of input event and target clock. Single-cycle pulse generation for target. 7.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 4. Boot mode when OTP BOOT_SRC bits are programmed Boot mode BOOT_SRC BOOT_SRC BOOT_SRC bit 3 bit 2 bit 1 BOOT_SRC Description bit 0 Pin state 0 0 0 0 Boot source is defined by the reset state of P1_1, P1_2, P2_8 pins, and P2_9. See Table 5. USART0 0 0 0 1 Boot from device connected to USART0 using pins P2_0 and P2_1.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Remark: Pin functions for SPIFI and SSP0 boot are different. 7.14 Memory mapping The memory map shown in Figure 5 and Figure 6 is global to both the Cortex-M4 and the Cortex-M0 processors and all SRAM is shared between both processors. Each processor uses its own ARM private bus memory map for the NVIC and other system functions. LPC4370 Product data sheet All information provided in this document is subject to legal disclaimers.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller LPC4370 4 GB 0xFFFF FFFF reserved 0xE010 0000 ARM private bus reserved SPIFI data 256 MB dynamic external memory DYCS3 256 MB dynamic external memory DYCS2 reserved peripheral bit band alias region reserved 0xE000 0000 0x8800 0000 0x8000 0000 0x7000 0000 0x6000 0000 0x4400 0000 0x4200 0000 0x4010 2000 SGPIO SPI reserved high-speed GPIO reserved reserved 0x2000 0000 0x1F00 0000 0x1E00 0000 0x1D00 0000 0x1C00 0000 12-bit ADC (ADCHS) 16
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 0x400E 5000 reserved 0x400E 4000 10-bit ADC1 0x400E 3000 10-bit ADC0 0x400E 2000 C_CAN0 0x400E 1000
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.15 One-Time Programmable (OTP) memory The OTP provides 64-bit + 256 bit of memory for general purpose use. 7.16 General Purpose I/O (GPIO) The LPC4370 provide 8 GPIO ports with up to 31 GPIO pins each. Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller In the two-counter case, the following operational elements are global to the SCT, but the last three can use match conditions from either counter: • • • • • 7.17.1.1 Clock selection Inputs Events Outputs Interrupts Features • • • • • • • • Two 16-bit counters or one 32-bit counter. Counter(s) clocked by bus clock or selected input. Up counter(s) or up-down counter(s). State variable allows sequencing across multiple counter cycles.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.18 AHB peripherals 7.18.1 General Purpose DMA (GPDMA) The DMA controller allows peripheral-to memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receives.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller After a few commands configure the interface at startup, the entire flash content is accessible as normal memory using byte, halfword, and word accesses by the processor and/or DMA channels. Erasure and programming are handled by simple sequences of commands.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller – Extended wait • Four chip selects for synchronous memory and four chip selects for static memory devices. • Power-saving modes dynamically control EMC_CKEOUT and EMC_CLK signals to SDRAMs. • Dynamic memory self-refresh mode controlled by software. • Controller supports 2048 (A0 to A10), 4096 (A0 to A11), and 8192 (A0 to A12) row address synchronous memory parts.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller • This module has its own, integrated DMA engine. • USB interface electrical test software included in ROM USB stack. 7.18.7 LCD controller Remark: The LCD controller is available on the LPC4370FET256 parts. See Table 2. The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT panels can be operated.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.18.8 Ethernet 7.18.8.1 Features • • • • 10/100 Mbit/s DMA support Power management remote wake-up frame and magic packet detection Supports both full-duplex and half-duplex operation – Supports CSMA/CD Protocol for half-duplex operation. – Supports IEEE 802.3x flow control for full-duplex operation. – Optional forwarding of received pause control frames to the user application in full-duplex operation.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.19.2 USART0/2/3 The LPC4370 contain three USARTs. In addition to standard transmit and receive data lines, the USARTs support a synchronous mode. The USARTs include a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.19.2.1 Features • • • • • Maximum UART data bit rate of 8 MBit/s. 16 B Receive and Transmit FIFOs.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.19.4.1 Features • Maximum SSP speed in full-duplex mode of 25 Mbit/s; for transmit only 50 Mbit/s (master) and 15 Mbit/s (slave).
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller The I2S-bus provides a standard communication interface for digital audio applications. The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S-bus connection has one master, which is always the master, and one slave. The I2S-bus interface provides a separate transmit and receive channel, each of which can operate as either a master or a slave. 7.19.6.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.20 Counter/timers and motor control 7.20.1 General purpose 32-bit timers/external event counters The LPC4370 include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.20.3.1 Features • • • • • • • • • • Tracks encoder position. Increments/decrements depending on direction. Programmable for 2 or 4 position counting. Velocity capture using built-in timer. Velocity compare function with “less than” interrupt. Uses 32-bit registers for position and velocity. Three position compare registers with interrupts. Index counter for revolution counting. Index compare register with interrupts.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller • Flag to indicate watchdog reset. • Programmable 24-bit timer with internal prescaler. • Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in multiples of Tcy(WDCLK)  4. 7.21 Analog peripherals 7.21.1 12-bit high-speed Analog-to-Digital Converter (ADCHS) 7.21.1.1 Features • • • • • • • • • • 12-bit high-speed ADC. Six single-sided input channels or one differential input channel.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.22 Peripherals in the RTC power domain 7.22.1 RTC The Real Time Clock (RTC) is a set of counters for measuring time when system power is on, and optionally when it is off. It uses very little power when its registers are not being accessed by the CPU, especially reduced power modes. The RTC is clocked by a separate 32 kHz oscillator that produces a 1 Hz internal time reference. The RTC is powered by its own power supply pin, VBAT. 7.22.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller digital and analog function, the ADC function select registers in the SCU enable the analog function. A separate set of analog I/Os for the ADCs and the DAC as well as most USB pins are located on separate pads and are not controlled through the SCU. In addition, the clock delay register for the SDRAM EMC_CLK pins and the registers that select the pin interrupts are located in the SCU. 7.23.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 s. 7.23.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller LPC43xx VDDIO to I/O pads to cores VSS REGULATOR to memories, peripherals, oscillators, PLLs VDDREG MAIN POWER DOMAIN ULTRA LOW-POWER REGULATOR VBAT to RTC domain peripherals RESET/WAKE-UP CONTROL to RTC I/O pads (Vps) RESET WAKEUP0/1/2/3 BACKUP REGISTERS RTCX1 RTCX2 32 kHz OSCILLATOR REAL-TIME CLOCK ALARM ALWAYS-ON/RTC POWER DOMAIN DAC VDDA VSSA ADC ADC POWER DOMAIN OTP VPP OTP POWER DOMAIN USB0_VDDA3V_DRIVER USB0_VDDA
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 6.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Wake-up from the Power-down modes, Deep-sleep, Power-down, and Deep power-down, is caused by an event on the WAKEUP pins or an event from the RTC or alarm timer. When waking up from Deep power-down mode, the part resets and attempts to boot. After booting, the M4 core is in active mode and both M0 cores remain in the reset state until the reset is released by software. 7.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 8. Limiting values Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD(REG)(3V3) regulator supply voltage (3.3 V) on pin VDDREG 0.5 3.6 V VDD(IO) input/output supply voltage on pin VDDIO 0.5 3.6 V VDDA(3V3) analog supply voltage (3.3 V) on pin VDDA 0.5 3.6 V VBAT battery supply voltage on pin VBAT 0.5 3.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 9. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb +  P D  R th  j – a   (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 10. Static characteristics Table 10. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Min Typ[1] Max Unit 2.2 - 3.6 V 2.2 - 3.6 V on pin VDDA 2.2 - 3.6 V on pins USB0_VDDA3V3_ DRIVER and USB0_VDDA3V3 3.0 3.3 3.6 V Conditions Supply pins VDD(IO) input/output supply voltage VDD(REG)(3V3) regulator supply voltage (3.3 V) VDDA(3V3) analog supply voltage (3.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 10. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol IBAT Parameter battery supply current Conditions VDD(REG)(3V3) = 3.3 V; VBAT = 3.6 V deep-sleep mode IDD(IO) I/O supply current power-down mode [8] deep power-down mode [8] deep sleep mode IDDA Analog supply current on pin VDDA; Typ[1] Max Unit - 2 - A - 2 - A - 2 - A - 1 - A - 1 - A [9] - 0.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 10. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VOH HIGH-level output voltage IOH = 6 mA VDD(IO)  0.4 - - V VOL LOW-level output voltage IOL = 6 mA - - 0.4 V IOH HIGH-level output current VOH = VDD(IO)  0.4 V 6 - - mA IOL LOW-level output current VOL = 0.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 10. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Ipd Parameter pull-down current Conditions VI = VDD(IO) [14] Min Typ[1] Max Unit - 62 - A - 62 - A - 10 - A [15] [16] Ipu pull-up current VI = 0 V [14] [15] [16] VDD(IO) < VI  5 V I/O pins - high drive strength: standard drive mode IOH HIGH-level output current VOH = VDD(IO)  0.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 10. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit ILL LOW-level leakage current VI = 0 V; on-chip pull-up resistor disabled - 3 - nA ILH HIGH-level leakage current VI = VDD(IO); on-chip pull-down resistor disabled - 3 - nA VI = 5 V - - 20 nA - 3 - nA 0 - 5.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 10. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Vhys hysteresis voltage VOL LOW-level output voltage IOLS = 3 mA ILI input leakage current VI = VDD(IO) [13] VI = 5 V Min Typ[1] Max Unit 0.1  VDD(IO) - - V - - 0.4 V - 4.5 - A - - 10 A Oscillator pins Vi(XTAL1) input voltage on pin XTAL1 0.5 - 1.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 10. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VOH HIGH-level output voltage (driven) for low-/full-speed RL of 15 k to GND 2.8 - 3.5 V Ctrans transceiver capacitance pin to GND - - 20 pF ZDRV driver output with 33  series resistor; impedance for driver steady state drive which is not high-speed capable 36 - 44.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 10.1 Power consumption 002aah611 100 IDD(REG)(3V3) IDD(REG)(3V3) (mA) (mA) 204 MHz 80 180 MHz 60 120 MHz 40 60 MHz 20 12 MHz 0 2.2 2.4 2.6 2.8 3 3.2 3.4 VDD(REG)(3V3) (V) 3.6 Conditions: Tamb = 25 C; active mode entered executing code while(1){} from SRAM; M0 cores in reset; internal pull-up resistors disabled; PLL1 enabled; IRC enabled; all peripherals disabled; all peripheral clocks disabled. Fig 8.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah613 100 IDD(REG)(3V3) IDD(REG)(3V3) (mA) (mA) 85 °C C 25 °C C -40 °C C 80 60 40 20 0 12 36 60 84 108 132 156 180 CCLK frequency (MHz) 204 Conditions: VDD(REG)(3V3) = 3.3 V; Active mode entered executing code while(1){} from SRAM;M0 cores in reset; internal pull-up resistors disabled; PLL1 enabled; IRC enabled; all peripherals disabled; all peripheral clocks disabled. Fig 10.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah154 300 IDD(REG)(3V3) )( (μA) 240 180 120 60 0 -40 -15 10 35 60 temperature (°C) 85 Conditions: VDD(REG)(3V3) = 3.3 V; VBAT floating; VDD(IO) = 3.3 V. Fig 12. Typical supply current versus temperature in Deep-sleep mode 002aah155 50 IDD(REG)(3V3) )( (μA) 40 30 20 10 0 -40 -15 10 35 60 temperature (°C) 85 Conditions: VDD(REG)(3V3) = 3.3 V; VBAT floating; VDD(IO) = 3.3 V. Fig 13.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah156 10 IDD(REG)(3V3) DD(REG (μA) 8 6 4 2 0 -40 -15 10 35 60 temperature (°C) 85 Conditions: VDD(REG)(3V3) = 3.3 V; VBAT floating; VDD(IO) = 3.3 V. Fig 14. Typical supply current versus temperature in Deep power-down mode 002aah150 80 IBAT (μA) 60 40 20 0 -0.4 -0.2 0 0.2 0.4 VBAT - VDD(REG)(3V3) (V) 0.6 Conditions: VDD(REG)(3V3) = 3.0 V; CCLK = 12 MHz. Fig 15.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah157 10 IBAT (μA) 8 6 VBAT = 3.6 V 3.0 V 2.2 V 4 2 0 -40 -15 10 35 60 temperature (°C) 85 Conditions: VDD(REG)(3V3), VDD(IO) floating. Fig 16. Typical battery supply versus temperature in Deep power-down mode 10.2 Peripheral power consumption The typical power consumption at T = 25 C for each individual peripheral is measured as follows: 1. Enable all branch clocks and measure the current IDD(REG)(3V3). 2.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 11. Peripheral power consumption Peripheral Branch clock IDD(REG)(3V3) in mA Branch clock Branch clock frequency = 48 MHz frequency = 96 MHz GPIO LPC4370 Product data sheet CLK_M4_GPIO 0.66 1.31 LCD CLK_M4_LCD 0.85 1.72 ETHERNET CLK_M4_ETHERNET 1.05 2.09 UART0 CLK_M4_UART0, CLK_APB0_UART0 0.3 0.38 UART1 CLK_M4_UART1, CLK_APB0_UART1 0.27 0.48 UART2 CLK_M4_UART2, CLK_APB2_UART2 0.27 0.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 12. Peripheral power consumption 12-bit ADCHS Peripheral Branch clock IDD(REG)(3V3) in mA Branch clock Branch clock frequency = 39 MHz frequency = 78 MHz Conditions ADCHS (12-bit ADC) CLK_ADCHS, CLK_M4_ADCH 1.1 2.3 Peripheral power consumption; no ADC conversions ADCHS (12-bit ADC) CLK_ADCHS, CLK_M4_ADCH 28.5 41.6 Peripheral power consumption; ADC converting samples at CLK_ADCHS frequency 10.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 10.4 Electrical pin characteristics 002aah030 15 -40 °C 25 °C 85 °C IOL (mA) 12 9 6 3 0 0 0.1 0.2 0.3 0.4 0.5 VOL (V) 0.6 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V. Fig 17. Normal-drive pins; typical LOW level output current IOL versus LOW level output voltage VOL 002aah039 3.6 VOH (V) 3.2 2.8 T = 85 °C 25 °C -40 °C 2.4 2.0 0 12 24 36 IOH (mA) Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V. Fig 18.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah040 15 -40 °C 25 °C 85 °C IOL (mA) 12 002aah041 25 IOL (mA) 20 9 15 6 10 3 5 0 -40 °C 25 °C 85 °C 0 0 0.1 0.2 0.3 0.4 0.5 VOL (V) 0.6 0 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; normal-drive; EHD = 0x0. 0.2 0.3 0.4 0.5 VOL (V) 0.6 Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; medium-drive; EHD = 0x1. 002aah043 40 IOL (mA) 0.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aah047 3.6 VOH (V) 002aah048 3.6 VOH (V) 3.2 3.2 -40 °C 25 °C 85 °C 2.8 -40 °C 25 °C 85 °C 2.8 2.4 2.4 2.0 2.0 0 8 16 24 0 16 32 IOH (mA) Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; normal-drive; EHD = 0x0. 002aah049 3.6 48 IOH (mA) VOH (V) Conditions: VDD(REG)(3V3) = VDD(IO) = 3.3 V; medium-drive; EHD = 0x1. 002aah050 3.6 VOH (V) 3.2 3.2 -40 °C 25 °C 85 °C 2.8 -40 °C 25 °C 85 °C 2.8 2.4 2.4 2.0 2.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 002aag625 +20 Ipu (μA) 0 -20 T = 25 °C -40 °C -40 -60 -80 0 1 2 3 4 5 VI (V) Conditions: VDD(IO)) = 3.3 V. Simulated values. Values at T = 25 C are typical values. Values at T = 40 C correspond to minimum values. Fig 21. Typical pull-up current Ipu versus input voltage VI 002aag626 120 Ipd (μA) 90 60 T =25 °C -40 °C 30 0 0 1 2 3 4 5 VI (V) Conditions: VDD(IO)) = 3.3 V. Simulated values.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11. Dynamic characteristics 11.1 Wake-up times Table 14.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.3 Crystal oscillator Table 16. Dynamic characteristic: oscillator Tamb = 40 C to +85 C; VDD(IO) over specified ranges; 2.2 V  VDD(REG)(3V3)  3.6 V.[1] Symbol Parameter Conditions Low-frequency mode (1 MHz - 20 tjit(per) period jitter time period jitter time Typ[2] Max Unit MHz)[5] 5 MHz crystal [3][4] - 13.2 - ps 10 MHz crystal - 6.6 - ps 15 MHz crystal - 4.8 - ps - 4.3 - ps - 3.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.6 I2C-bus Table 19. Dynamic characteristic: I2C-bus pins Tamb = 40 C to +85 C; 2.2 V  VDD(REG)(3V3)  3.6 V.[1] Symbol Parameter Conditions Min Max Unit fSCL SCL clock frequency Standard-mode 0 100 kHz [3][4][5][6] fall time tf Fast-mode 0 400 kHz Fast-mode Plus 0 1 MHz of both SDA and SCL signals - 300 ns Fast-mode 20 + 0.1  Cb 300 ns Fast-mode Plus - 120 ns Standard-mode 4.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller tf SDA tSU;DAT 70 % 30 % 70 % 30 % tHD;DAT tf 70 % 30 % SCL tVD;DAT tHIGH 70 % 30 % 70 % 30 % 70 % 30 % tLOW 1 / fSCL S 002aaf425 Fig 24. I2C-bus pins clock timing 11.7 I2S-bus interface Table 20. Dynamic characteristics: I2S-bus interface pins Tamb = 25 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. Conditions and data refer to I2S0 and I2S1 pins. Simulated values.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Tcy(clk) tf tr I2Sx_TX_SCK tWH tWL I2Sx_TX_SDA tv(Q) I2Sx_TX_WS 002aag497 tv(Q) Fig 25. I2S-bus timing (transmit) Tcy(clk) tf tr I2Sx_RX_SCK tWH tWL I2Sx_RX_SDA tsu(D) th(D) I2Sx_RX_WS tsu(D) 002aag498 tsu(D) Fig 26. I2S-bus timing (receive) 11.8 USART interface Table 21. Dynamic characteristics: USART interface Tamb = 25 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; CL = 20 pF. Simulated values.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.9 SSP interface Table 22. Dynamic characteristics: SSP pins in SPI mode Tamb = 25 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. Simulated values. Symbol Tcy(clk) Parameter clock cycle time Conditions Min Typ Max Unit - 40 - ns when only transmitting - 20 - ns in SPI mode 13.3 - - ns full-duplex mode [1] SSP master tDS data set-up time tDH data hold time in SPI mode 3.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.10 SPI interface Table 23. Dynamic characteristics: SPI Tamb = 40 C to +85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. Simulated values. Symbol Parameter Tcy(PCLK) PCLK cycle time Tcy(clk) Conditions Min Typ Max 5 [1] clock cycle time Unit ns 40 - - ns Master tDS data set-up time 7.2 - - ns tDH data hold time 0 - - ns tv(Q) data output valid time - - 3.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Tcy(clk) SCK (CPOL = 0) SCK (CPOL = 1) tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO th(Q) DATA VALID tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO DATA VALID CPHA = 1 DATA VALID th(Q) CPHA = 0 DATA VALID 002aae830 Fig 28. SSP slave timing in SPI mode LPC4370 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 October 2013 © NXP B.V. 2013. All rights reserved.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.12 SPIFI Table 24. Dynamic characteristics: SPIFI Tamb = 40 C to 85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. CL = 10 pF. Simulated values. Symbol Parameter Min Max Unit Tcy(clk) clock cycle time 9.6 - ns tDS data set-up time 3.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 25. Dynamic characteristics: SGPIO Tamb = 40 C to +85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. Simulated values.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.14 External memory interface Table 26. Dynamic characteristics: Static asynchronous external memory interface CL = 22 pF for EMC_Dn CL = 20 pF for all others; Tamb = 40 C to 85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; values guaranteed by design. Timing parameters are given for single memory access cycles.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 26. Dynamic characteristics: Static asynchronous external memory interface …continued CL = 22 pF for EMC_Dn CL = 20 pF for all others; Tamb = 40 C to 85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V; values guaranteed by design. Timing parameters are given for single memory access cycles. In a normal read operation, the EMC changes the address while CS is asserted which results in multiple memory accesses.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller EMC_An tCSLAV tCSLAV tOEHANV tCSHEOW EMC_CSn tCSLOEL tOELOEH EMC_OE tCSLBLSL tCSHOEH tCSLBLSL EMC_BLSn tCSHBLSH tCSLWEL tWELWEH tWEHEOW EMC_WE tBLSHDNV tam tCSHEOR th(D) tCSLSOR tCSLDV tWEHDNV EMC_Dn SOR EOR EOW 002aag700 Fig 32. External static memory read/write access (PB = 1) LPC4370 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 October 2013 © NXP B.V.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 27. Dynamic characteristics: Dynamic external memory interface Simulated data over temperature and process range; CL = 10 pF for EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE, EMC_An; CL = 9 pF for EMC_Dn; CL = 5 pF for EMC_DQMOUTn, EMC_CLKn, EMC_CKEOUTn; Tamb = 40 C to 85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; VDD(IO) =3.3 V  10 %; RD = 1 (see LPC43xx User manual); EMC_CLKn delays CLK0_DELAY = CLK1_DELAY = CLK2_DELAY = CLK3_DELAY = 0.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller EMC_CLKn delay > 0 EMC_CLKn delay td; programmable CLKn_DELAY Tcy(clk) EMC_CLKn delay = 0 td(xV) - td EMC_DYCSn, EMC_RAS, EMC_CAS, EMC_WE, EMC_CKEOUTn, EMC_A[22:0], EMC_DQMOUTn td(xV) th(x) - td th(x) td(QV) - td td(QV) th(Q) - td th(Q) EMC_D[31:0] write tsu(D) th(D) EMC_D[31:0] read; delay > 0 tsu(D) th(D) EMC_D[31:0] read; delay = 0 002aag703 For the programmable EMC_CLK[3:0] clock delays CLKn_DELAY, see Table 28.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.15 USB interface Table 29. Dynamic characteristics: USB0 and USB1 pins (full-speed) CL = 50 pF; Rpu = 1.5 k on D+ to VDD(IO); 3.0 V  VDD(IO)  3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 % to 90 % 8.5 - 13.8 ns tf fall time 10 % to 90 % 7.7 - 13.7 ns tFRFM differential rise and fall time matching tr / tf - - 109 % VCRS output signal crossover voltage 1.3 - 2.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 30. Symbol Static characteristics: USB0 PHY pins[1] Parameter Conditions Min Typ Max Unit - 68 - mW - 18 - mA High-speed mode Pcons [2] power consumption IDDA(3V3) analog supply current (3.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 31. Dynamic characteristics: Ethernet Tamb = 40 C to 85 C; 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V. Values guaranteed by design.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 11.17 SD/MMC Table 32. Dynamic characteristics: SD/MMC Tamb = 40 C to 85 C, 2.2 V  VDD(REG)(3V3)  3.6 V; 2.7 V  VDD(IO)  3.6 V, CL = 20 pF. Simulated values. SAMPLE_DELAY = 0x8, DRV_DELAY = 0xF in the SDDELAY register (see the LPC18xx user manual UM10430). Symbol Parameter Conditions fclk clock frequency tr rise time tf fall time tsu(D) data input set-up time th(D) td(QV) th(Q) Min Max Unit 52 MHz 0.5 2 ns 0.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 12. ADC/DAC electrical characteristics Table 34. 12-bit ADC characteristics VDDA(3V3) over specified ranges; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter VDC DC input common mode level Cin input capacitance Ri Conditions Min Typ Max Unit 0.1 0.5 0.9 V single ended - 4.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 35. 10-bit ADC characteristics VDDA(3V3) over specified ranges; Tamb = 40 C to +85 C; ADC frequency 4.5 MHz; unless otherwise specified. Symbol Parameter VIA Cia ED differential linearity error EL(adj) Conditions Min Typ Max analog input voltage 0 - VDDA(3V3) V analog input capacitance - - 2 pF [1][2] - 0.8 - LSB - 1.0 - LSB integral non-linearity [3] - 0.8 - LSB - 1.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = VDDA(3V3) − VSSA 1024 002aaf959 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Rvsi LPC43xx 2 kΩ (analog pin) 2.2 kΩ (multiplexed pin) ADC0_n/ADC1_n Rs ADC COMPARATOR Cia = 2 pF VEXT VSS 002aag704 Rs  1/((7  fclk(ADC)  Cia)  2 k Fig 38. ADC interface to pins Table 36. DAC characteristics VDDA(3V3) over specified ranges; Tamb = 40 C to +85 C; unless otherwise specified Symbol ED Parameter Conditions differential linearity error 2.7 V  VDDA(3V3)  3.6 V [1] 2.2 V  VDDA(3V3) < 2.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 13. Application information 13.1 LCD panel signal usage Table 37.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 38.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 39.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 40. Recommended values for CX1/X2 in oscillation mode (crystal and external components parameters) low frequency mode Fundamental oscillation frequency Maximum crystal series resistance RS External load capacitors CX1, CX2 12 MHz < 160  18 pF, 18 pF < 160  39 pF, 39 pF 16 MHz < 120  18 pF, 18 pF < 80  33 pF, 33 pF <100  18 pF, 18 pF < 80  33 pF, 33 pF 20 MHz Table 41.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 13.3 RTC oscillator In the RTC oscillator circuit, only the crystal (XTAL) and the capacitances CRTCX1 and CRTCX2 need to be connected externally. Typical capacitance values for CRTCX1 and CRTCX2 are CRTCX1/2 = 20 (typical)  4 pF. An external clock can be connected to RTCX1 if RTCX2 is left open. The recommended amplitude of the clock signal is Vi(RMS) = 100 mV to 200 mV with a coupling capacitance of 5 pF to 10 pF.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller VDDIO ESD enable output driver data output from core PIN slew rate bit EHS input buffer enable bit EZI data input to core glitch filter filter select bit ZIF pull-up enable bit EPUN ESD pull-down enable bit EPD analog I/O VSSIO 002aah028 The glitch filter rejects pulses of typical 12 ns width. Fig 42. Standard I/O pin configuration with analog input 13.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 13.7 Minimizing interference between digital signals and 12-bit ADC signals To reduce interference from digital signals to the high-speed 12-bit ADC inputs, do not configure digital pins that are pinned out close to the ADC signals as outputs when using the 12-bit ADC. For the BGA256 package, the pins with interfering signals are shown in Table 42. Table 42.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller The allowed input range for Vin_neg, if supplied externally on pin ADCHS_NEG, is 350 mV  Vin_neg  900 mV. See Figure 45. Vin_pos (mV) 1200 800 750 450 400 0 Vin_neg (mV) 400 350 800 850 aaa-009654 Fig 45.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 13.8.1 Inverting single-ended circuit For the inverting single-ended circuit only one op-amp is needed. A 1.24 V shunt voltage reference is used for creating an offset voltage of 450 mV. The disadvantage is that the signal output of the circuit is inverted. However, this can be easily solved in software by subtracting the ADC output from 4095, which is the maximum value of the 12-bit result.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 13.8.2 Non-inverting single-ended circuit with gain = 1 The advantage of having a non-inverting circuit comes at the cost of adding an additional op-amp for a high-impedance voltage reference to prevent the reference level being influenced by the input signal. This circuit is recommended for an input voltage from 100 mV to 800 mV using the internal negative reference voltage.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 13.8.3 Non-inverting single-ended circuit for input 0 V to 3.3 V The advantage of having a non-inverting circuit comes at the cost of adding an additional op-amp for a high-impedance voltage reference to prevent the reference level being influenced by the input signal. This circuit is recommended for an input voltage from 0 V to 3.3 V using the internal negative reference voltage.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 14.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm B D SOT926-1 A ball A1 index area A2 E A A1 detail X e1 e ∅v ∅w b 1/2 e C M M C A B C y y1 C K J e H G F e2 E D 1/2 e C B A ball A1 index area 1 2 3 4 5 6 7 8 9 10 X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 A2 b D E e e1 e2 v w y y1 mm 1.2 0.4 0.3 0.8 0.65 0.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 15. Soldering Footprint information for reflow soldering of LBGA256 package SOT740-2 Hx P P Hy see detail X Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste SL SP occupied area SR solder resist detail X DIMENSIONS in mm P SL SP SR 1.00 0.450 0.450 0.600 Hx Hy 17.500 17.500 sot740-2_fr Fig 51.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Footprint information for reflow soldering of TFBGA100 package SOT926-1 Hx P P Hy see detail X Generic footprint pattern Refer to the package outline drawing for actual layout solder land solder paste deposit solder land plus solder paste SL SP occupied area SR solder resist detail X DIMENSIONS in mm P SL SP SR Hx Hy 0.80 0.330 0.400 0.480 9.400 9.400 sot926-1_fr Fig 52.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 16. Abbreviations Table 43.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 17. References [1] LPC4370 Product data sheet LPC4370 Errata sheet. All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 October 2013 © NXP B.V. 2013. All rights reserved.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 18. Revision history Table 44. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC4370 v.2 20131021 - Modifications: LPC4371_70 v.1.1 Modifications: Product data sheet LPC4371_70 v.1.1 • • • • Part LPC4371 removed. • • • • • • OTP memory size available for general-purpose use corrected. • • • Section 13.8 “12-bit ADCHS input selection” added. LCD added to part LPC4370.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Table 44. Revision history …continued Document ID Modifications: Modifications: LPC4371_70 v.1 Modifications: LPC4370 Product data sheet Release date Data sheet status Change notice Supersedes • Parameter ILH (High-level leakage current) for condition VI = 5 V changed to 20 nA (max). See Table 10. • Parameter VDDA(3V3) added for pins USB0_VDDA3V3_DRIVER and USB0_VDDA3V3 in Table 10.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 5 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 5 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
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LPC4370 NXP Semiconductors 32-bit ARM Cortex-M4/M0 microcontroller 7.23.2 System Control Unit (SCU). . . . . . . . . . . . . . . 79 7.23.3 Clock Generation Unit (CGU) . . . . . . . . . . . . . 80 7.23.4 Internal RC oscillator (IRC). . . . . . . . . . . . . . . 80 7.23.5 PLL0USB (for USB0) . . . . . . . . . . . . . . . . . . . 80 7.23.6 PLL0AUDIO (for audio) . . . . . . . . . . . . . . . . . 80 7.23.7 System PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . 80 7.23.8 Reset Generation Unit (RGU). . .