Datasheet

LPC4370 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 21 October 2013 100 of 150
NXP Semiconductors
LPC4370
32-bit ARM Cortex-M4/M0 microcontroller
10.3 BOD static characteristics
[1] Interrupt and reset levels are selected by writing to the BODLV1/2 bits in the control register CREGE0, see
the LPC43xx user manual.
Table 12. Peripheral power consumption 12-bit ADCHS
Peripheral Branch clock I
DD(REG)(3V3)
in mA
Branch clock
frequency = 39 MHz
Branch clock
frequency = 78 MHz
Conditions
ADCHS (12-bit ADC) CLK_ADCHS,
CLK_M4_ADCH
1.1 2.3 Peripheral power consumption;
no ADC conversions
ADCHS (12-bit ADC) CLK_ADCHS,
CLK_M4_ADCH
28.5 41.6 Peripheral power consumption;
ADC converting samples at
CLK_ADCHS frequency
Table 13. BOD static characteristics
[1]
T
amb
=25  C; simulated values for nominal processing.
Symbol Parameter Conditions Min Typ Max Unit
V
th
threshold voltage interrupt level 0
assertion - 2.75 - V
de-assertion - 2.92 - V
interrupt level 1
assertion - 2.85 - V
de-assertion - 3.00 - V
interrupt level 2
assertion - 2.95 - V
de-assertion - 3.12 - V
interrupt level 3
assertion - 3.05 - V
de-assertion - 3.19 - V
reset level 0
assertion - 1.70 - V
de-assertion - 1.85 - V
reset level 1
assertion - 1.80 - V
de-assertion - 1.95 - V
reset level 2
assertion - 1.90 - V
de-assertion - 2.05 - V
reset level 3
assertion - 2.00 - V
de-assertion - 2.15 - V