Datasheet

LPC4370 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 21 October 2013 111 of 150
NXP Semiconductors
LPC4370
32-bit ARM Cortex-M4/M0 microcontroller
11.10 SPI interface
[1] T
cy(clk)
= 8/BASE_SPI_CLK. Tcy(PCLK) = 1/BASE_SPI_CLK.
11.11 SSP/SPI timing diagrams
Table 23. Dynamic characteristics: SPI
T
amb
=  40  C to +85  C; 2.2 V  V
DD(REG)(3V3)
 3.6 V; 2.7 V  V
DD(IO)
 3.6 V. Simulated values.
Symbol Parameter Conditions Min Typ Max Unit
T
cy(PCLK)
PCLK cycle time 5 ns
T
cy(clk)
clock cycle time
[1]
40 - - ns
Master
t
DS
data set-up time 7.2 - - ns
t
DH
data hold time 0 - - ns
t
v(Q)
data output valid time - - 3.7 ns
t
h(Q)
data output hold time - - 1.2 ns
Slave
t
DS
data set-up time 1.2 - - ns
t
DH
data hold time 3 x T
cy(PCLK)
+ 0.54 - - ns
t
v(Q)
data output valid time - - 3 x T
cy(PCLK)
+ 9.7 ns
t
h(Q)
data output hold time - - 2 x T
cy(PCLK)
+ 7.1 ns
Fig 27. SSP master timing in SPI mode
SCK (CPOL = 0)
MOSI
MISO
T
cy(clk)
t
DS
t
DH
t
v(Q)
DATA VALID DATA VALID
t
h(Q)
SCK (CPOL = 1)
DATA VALID
DATA VALID
MOSI
MISO
t
DS
t
DH
DATA VALID DATA VALID
t
h(Q)
DATA VALID
DATA VALID
t
v(Q)
CPHA = 1
CPHA = 0
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