Datasheet

LPC4370 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 21 October 2013 125 of 150
NXP Semiconductors
LPC4370
32-bit ARM Cortex-M4/M0 microcontroller
[1] The ADC is monotonic, there are no missing codes.
[2] The differential linearity error (E
D
) is the difference between the actual step width and the ideal step width. See Figure 37.
[3] The integral non-linearity (E
L(adj)
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
appropriate adjustment of gain and offset errors. See Figure 37
.
[4] The offset error (E
O
) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the
ideal curve. See Figure 37
.
[5] The gain error (E
G
) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset
error, and the straight line which fits the ideal transfer curve. See Figure 37
.
[6] The absolute error (E
T
) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
ADC and the ideal transfer curve. See Figure 37
.
[7] T
amb
= 25 C; maximum sampling frequency f
s
= 4.5 MHz and analog input capacitance C
ia
= 2 pF.
[8] Input resistance R
i
depends on the sampling frequency fs: R
i
= 2 k + 1 / (f
s
 C
ia
).
Table 35. 10-bit ADC characteristics
V
DDA(3V3)
over specified ranges; T
amb
=  40  C to +85  C; ADC frequency 4.5 MHz; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
V
IA
analog input voltage 0 - V
DDA(3V3)
V
C
ia
analog input
capacitance
-- 2 pF
E
D
differential linearity error
[1][2]
- 0.8 - LSB
- 1.0 - LSB
E
L(adj)
integral non-linearity
[3]
- 0.8 - LSB
- 1.5 - LSB
E
O
offset error
[4]
- 0.15 - LSB
- 0.15 - LSB
E
G
gain error
[5]
- 0.3 - %
- 0.35 - %
E
T
absolute error
[6]
- 3- LSB
- 4- LSB
R
vsi
voltage source interface
resistance
see Figure 38 -- 1/(7  f
clk(ADC)
 C
ia
)
k
R
i
input resistance
[7][8]
-- 1.2 M
f
clk(ADC)
ADC clock frequency - - 4.5 MHz
f
c(ADC)
ADC conversion
frequency
10-bit resolution; 11 clock
cycles
- - 400 kSamples/s
2-bit resolution; 3 clock
cycles
1.5 MSamples/s