Datasheet
LPC4370 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 21 October 2013 145 of 150
NXP Semiconductors
LPC4370
32-bit ARM Cortex-M4/M0 microcontroller
18. Revision history
Table 44. Revision history
Document ID Release date Data sheet status Change notice Supersedes
LPC4370 v.2 20131021 Product data sheet - LPC4371_70 v.1.1
Modifications:
• Part LPC4371 removed.
• LCD added to part LPC4370.
• Data sheet title changed to LPC4370.
• VADC renamed to ADCHS throughout the document. Pin VADC_NEG renamed to
ADCHS_NEG.
• OTP memory size available for general-purpose use corrected.
• SD/MMC timing parameters corrected. See Table 32.
• Band gap characteristics removed.
• Description of RESET pin updated in Table 3.
• Table note 9 added in Table 10.
• Minimum value of parameter V
DC
changed to 0.1 V. See Table 34 “12-bit ADC
characteristics”.
• Section 13.8 “12-bit ADCHS input selection” added.
• Table 12 “Peripheral power consumption 12-bit ADCHS” added.
• Data sheet status changed to Product data sheet.
LPC4371_70 v.1.1 02112013 Objective data sheet - LPC4371_70 v.1
Modifications:
• SSP0 boot pin functions corrected in Table 5 and Table 4. Pin P3_3 = SSP0_SCK, pin
P3_6 = SSP0_SSEL, pin P3_7 = SSP0_MISO, pin P3_8 = SSP0_MOSI.
• Section 13.7 “Minimizing interference between digital signals and 12-bit ADC signals”
added. Pin description table updated with Table note 13.
• TFBGA100 package added.
• Table 7 “Limiting values” updated.
• Parameter name I
DD(ADC)
changed to I
DDA
in Table 10.
• Minimum value for parameter V
IL
changed to 0 V in Table 10.
• Added note to limit data in Table 25 “Dynamic characteristics: Static asynchronous
external memory interface” to single memory accesses.
• Table 23 “Dynamic characteristics: SPIFI” added.
• Power consumption in active mode corrected. See parameter I
DD(REG)(3V3)
in Table 10
and graphs Figure 8, Figure 9, and Figure 10.
• Band gap characteristics added. See Table 13 and Figure 17.
• Value of parameter I
DD(REG)(3V3)
in deep power-down increased to 0.03 μA in
Table 10.
• Value of parameter I
DD(IO)
in deep power-down increased to 0.05 μA in Table 10.
• Figure 4 “AHB multilayer matrix master and slave connections” updated.