Datasheet

LPC4370 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 21 October 2013 146 of 150
NXP Semiconductors
LPC4370
32-bit ARM Cortex-M4/M0 microcontroller
Modifications: • Parameter I
LH
(High-level leakage current) for condition V
I
= 5 V changed to 20 nA
(max). See Table 10.
• Parameter V
DDA(3V3)
added for pins USB0_VDDA3V3_DRIVER and
USB0_VDDA3V3 in Table 10.
• Maximum speed for SPI added in Section 7.19.3.
• SPIFI speed changed to 53 MB/s.
• Section 7.23.9.1 “Memory retention in Power-down modes” added.
• I
DD(REG)(3V3)
for Power-down mode with M0SUB SRAM memory retained added in
Table 10.
• SPI timing data added. See Table 22.
Modifications:
• SGPIO timing data added. See Table 24.
• SPI and SGPIO peripheral power consumption added in Table 11.
• Corrected max voltage on pins USB0_DP, USB0_DM, USB0_VBUS, USB1_DP, and
USB1_DM in Table 7 and Table 10 to be consistent with USB specifications.
LPC4371_70 v.1 20120808 Objective data sheet - LPC43A50_30_20 v.0.5
Modifications:
• Power consumption data in Section 10 “Static characteristics” updated.
• BOD levels updated in Table 12.
• 12-bit ADC characterisation added in Table 33.
• Pinout corrected for the LBGA256 package in Table 3: Function ADCHS_3 moved to
ball A5 and Function ADCHS_NEG moved to ball B5.
• SWD removed for ARM Cortex-M0 core.
Table 44. Revision history
…continued
Document ID Release date Data sheet status Change notice Supersedes