Datasheet
LPC4370 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 21 October 2013 2 of 150
NXP Semiconductors
LPC4370
32-bit ARM Cortex-M4/M0 microcontroller
JTAG and built-in NVIC.
Cortex-M0 subsystem
ARM Cortex-M0 processor controlling the SPI and SGPIO peripherals residing on
a separate AHB multilayer matrix with direct access to 2 kB + 16 kB of SRAM.
Running at frequencies of up to 204 MHz.
Connected via a core-to-core bridge to the main AHB multilayer matrix and the
main ARM Cortex-M4 processor.
JTAG and built-in NVIC.
On-chip memory
264 kB SRAM for code and data use on the main AHB multilayer matrix plus 18 kB
of SRAM on the Cortex-M0 subsystem.
Multiple SRAM blocks with separate bus access. Two SRAM blocks can be
powered down individually.
64 kB ROM containing boot code and on-chip software drivers.
64-bit + 256 bit general-purpose One-Time Programmable (OTP) memory.
Configurable digital peripherals
Serial GPIO (SGPIO) interface.
State Configurable Timer (SCT) subsystem on AHB.
Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and
outputs to event driven peripherals like the timers, SCT, and ADC0/1.
Serial interfaces
Quad SPI Flash Interface (SPIFI) with four lanes and up to 52 MB per second.
10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high
throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time
stamping (IEEE 1588-2008 v2).
One High-speed USB 2.0 Host/Device/OTG interface with DMA support and
on-chip high-speed PHY.
One High-speed USB 2.0 Host/Device interface with DMA support, on-chip
full-speed PHY and ULPI interface to external high-speed PHY.
USB interface electrical test software included in ROM USB stack.
One 550 UART with DMA support and full modem interface.
Three 550 USARTs with DMA and synchronous mode support and a smart card
interface conforming to ISO7816 specification. One USART with IrDA interface.
Two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller
excludes operation of all other peripherals connected to the same bus bridge. See
Figure 1
and Ref. 1.
Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA
support.
One SPI controller.
One Fast-mode Plus I
2
C-bus interface with monitor mode and with open-drain I/O
pins conforming to the full I
2
C-bus specification. Supports data rates of up to
1Mbit/s.
One standard I
2
C-bus interface with monitor mode and with standard I/O pins.
Two I
2
S interfaces, each with DMA support and with one input and one output.
Digital peripherals
External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,
and SDRAM devices.