Datasheet

LPC4370 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 21 October 2013 55 of 150
NXP Semiconductors
LPC4370
32-bit ARM Cortex-M4/M0 microcontroller
[1] - = not pinned out.
[2] I = input, O = output, AI/O analog input/output, IA = inactive; PU = pull-up enabled (weak pull-up resistor pulls up pin to V
DD(IO)
); F =
floating. Reset state reflects the pin state at reset without boot code operation.
[3] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if V
DD(IO)
present; if V
DD(IO)
not present, do not exceed 3.3 V); provides digital I/O
functions with TTL levels and hysteresis; normal drive strength.
[4] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if V
DD(IO)
present; if V
DD(IO)
not present, do not exceed 3.3 V) providing digital I/O
functions with TTL levels, and hysteresis; high drive strength.
[5] 5 V tolerant pad with 15 ns glitch filter (5 V tolerant if V
DD(IO)
present; if V
DD(IO)
not present, do not exceed 3.3 V) providing high-speed
digital I/O functions with TTL levels and hysteresis.
VDDIO D7,
E12,
F7,
F8,
G10,
H10,
J6,
J7,
K7,
L9,
L10,
N7,
N13
F10,
K5
- - I/O power supply. Tie the VDDREG and VDDIO pins to a common power
supply to ensure the same ramp-up time for both supply voltages.
VDD - - Power supply for main regulator, I/O, and OTP.
VSS G9,
H7,
J10,
J11,
K8
- - - Ground.
VSSIO C4,
D13,
G6,
G7,
G8,
H8,
H9,
J8,
J9,
K9,
K10,
M13,
P7,
P13
C8,
D4,
D5,
G8,
J3,
J6
- - Ground.
VSSA B2 C2 - - Analog ground.
Not connected
-B9---n.c.
Table 3. Pin description
…continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
LBGA256 TFBGA100 Reset state [2] Type
Description