Datasheet

Product data sheet Rev. 2 — 21 October 2013 58 of 150

NXP Semiconductors

LPC4370

32-bit ARM Cortex-M4/M0 microcontroller

One of the two SRAM blocks connected to the subsystem AHB matrix is typically used for

code running on the M0 subsystem and the other SRAM block for data. This allows other

bus masters to access the data SRAM without interrupting the M0 processor instruction

fetches and thereby stalling the M0 subsystem.

The M0 subsystem matrix runs at an asynchronous speed from the main matrix. This

allows to operate the SGPIO at any desired frequency. The M0 subsystem can control the

SGPIO in a deterministic way, without incurring latency that occurs when the M4 controls

the SGPIO through a bridge.

7.4 Interprocessor communication

The ARM Cortex-M4 and ARM Cortex-M0 interprocessor communication is based on

using shared SRAM as mailbox and one processor raising an interrupt on the other

processor's NVIC, for example after it has delivered a new message in the mailbox. The

receiving processor can reply by raising an interrupt on the sending processor's NVIC to

acknowledge the message.