Datasheet

LPC4370 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 21 October 2013 6 of 150
NXP Semiconductors
LPC4370
32-bit ARM Cortex-M4/M0 microcontroller
5. Block diagram
(1) Not available on all parts (see Tab le 2).
Fig 1. LPC4370 Block diagram
ARM
CORTEX-M4
TEST/DEBUG
INTERFACE
I-code bus D-code bus system bus
DMA LCD
(1)
SD/
MMC
ETHERNET
10/100
MAC
IEEE 1588
HIGH-SPEED
USB0
HOST/
DEVICE/OTG
HIGH-SPEED
USB1
HOST/DEVICE
EMC
HIGH-SPEED PHY
32 kB AHB SRAM
16 +16 kB AHB SRAM
SPIFI
12-bit ADC (ADCHS)
HS GPIO
SCT
64 kB ROM
I
2
C0
I
2
S0
I
2
S1
C_CAN1
MOTOR
CONTROL
PWM
TIMER3
TIMER2
USART2
USART3
SSP1
RI TIMER
QEI
GIMA
BRIDGE 0 BRIDGE 1 BRIDGE 2 BRIDGE 3 BRIDGE
AHB MULTILAYER MATRIX
LPC4370
128 kB LOCAL SRAM
72 kB LOCAL SRAM
10-bit ADC0
10-bit ADC1
C_CAN0
I
2
C1
10-bit DAC
BRIDGE
RGU
CCU2
CGU
CCU1
ALARM TIMER
CONFIGURATION
REGISTERS
OTP MEMORY
EVENT ROUTER
POWER MODE CONTROL
12 MHz IRC
RTC POWER DOMAIN
BACKUP REGISTERS
RTC OSC
RTC
002aag606
slaves
ARM
CORTEX-M0
TEST/DEBUG
INTERFACE
= connected to GPDMA
GPIO
INTERRUPTS
GPIO GROUP0
INTERRUPT
GPIO GROUP1
INTERRUPT
WWDT
USART0
UART1
SSP0
TIMER0
TIMER1
SCU
CORE-CORE
BRIDGE
SPI
SGPIO
SUBSYSTEM AHB MULTILAYER MATRIX
masters
masters
master
ARM
CORTEX-M0
SUBSYSTEM
TEST/DEBUG
INTERFACE
slaves
2 kB LOCAL SRAM
16 kB LOCAL SRAM
system
bus
MPU
FPU