Datasheet

Product data sheet Rev. 2 — 21 October 2013 60 of 150

NXP Semiconductors

LPC4370

32-bit ARM Cortex-M4/M0 microcontroller

Each ARM Cortex-M0 coprocessor has its own NVIC with 32 vectored interrupts. Most

peripheral interrupts are shared between the two Cortex-M0cores and the Cortex-M4

NVICs.

7.6.1 Features

• ARM Cortex-M4 NVIC:

– Controls system exceptions and peripheral interrupts.

– Up to 53 vectored interrupts.

– Eight programmable interrupt priority levels with hardware priority level masking.

– Relocatable vector table.

– Non-Maskable Interrupt (NMI).

– Software interrupt generation.

• ARM Cortex-M0 and ARM Cortex-M0 subsystem NVIC:

– Control system exceptions and peripheral interrupts.

– Up to 32 vectored interrupts.

– Four programmable priority levels with hardware priority level masking.

7.6.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several

interrupt flags. Individual interrupt flags may also represent more than one interrupt

source.

7.7 System Tick timer (SysTick)

The ARM Cortex-M4 includes a system tick timer (SYSTICK) that is intended to generate

a dedicated SYSTICK exception at a 10 ms interval.

7.8 Event router

The event router combines various internal signals, interrupts, and the external interrupt

pins (WAKEUP[3:0]) to create an interrupt in the NVIC if enabled and to create a wake-up

signal to the ARM core and the CCU for waking up from Sleep, Deep-sleep, Power-down,

and Deep power-down modes. Individual events can be configured as edge or level

sensitive and can be enabled or disabled in the event router. The event router can be

battery powered.

The following events if enabled in the event router can create a wake-up signal and/or an

interrupt:

• External pins WAKEUP0/1/2/3 and RESET

• Alarm timer, RTC, WWDT, BOD interrupts

• C_CAN and QEI interrupts

• Ethernet, USB0, USB1 signals

• Selected outputs of combined timers (SCT and timer0/1/3)