Datasheet

LPC4370 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 21 October 2013 67 of 150
NXP Semiconductors
LPC4370
32-bit ARM Cortex-M4/M0 microcontroller
In the two-counter case, the following operational elements are global to the SCT, but the
last three can use match conditions from either counter:
• Clock selection
• Inputs
• Events
• Outputs
• Interrupts
7.17.1.1 Features
• Two 16-bit counters or one 32-bit counter.
• Counter(s) clocked by bus clock or selected input.
• Up counter(s) or up-down counter(s).
• State variable allows sequencing across multiple counter cycles.
• Event combines input or output condition and/or counter match in a specified state.
• Events control outputs and interrupts.
• Selected event(s) can limit, halt, start, or stop a counter.
• Supports:
– 8 inputs (one input connected internally)
– 16 outputs
– 16 match/capture registers
– 16 events
– 32 states
7.17.2 Serial GPIO (SGPIO)
The Serial GPIOs offer standard GPIO functionality enhanced with features to accelerate
serial stream processing.
7.17.2.1 Features
• Each SGPIO input/output slice can be used to perform a serial to parallel or parallel to
serial data conversion.
• 16 SGPIO input/output slices each with a 32-bit FIFO that can shift the input value
from a pin or an output value to a pin with every cycle of a shift clock.
• Each slice is double-buffered.
• Interrupt is generated on a full FIFO, shift clock, or pattern match.
• Slices can be concatenated to increase buffer size.
• Each slice has a 32-bit pattern match filter.