Datasheet

LPC4370 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 21 October 2013 81 of 150
NXP Semiconductors
LPC4370
32-bit ARM Cortex-M4/M0 microcontroller
clock. Since the minimum output divider value is 2, it is insured that the PLL output has a
50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be
enabled by software. The program must configure and activate the PLL, wait for the PLL
to lock, and then connect to the PLL as a clock source. The PLL settling time is 100 s.
7.23.8 Reset Generation Unit (RGU)
The RGU allows generation of independent reset signals for individual blocks and
peripherals on the LPC4370.
7.23.9 Power control
The LPC4370 feature several independent power domains to control power to the core
and the peripherals (see Figure 7
). The RTC and its associated peripherals (the alarm
timer, the CREG block, the OTP controller, the back-up registers, and the event router)
are located in the RTC power-domain which can be powered by a battery supply or the
main regulator. A power selector switch ensures that the RTC block is always powered on.