Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SO 20 32-Bit 30 MHz I/O number 18

1. General description

The LPC81xM are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at

CPU frequencies of up to 30 MHz. The LPC81xM support up to 16 kB of flash memory

and 4 kB of SRAM.

The peripheral complement of the LPC81xM includes a CRC engine, one I

C-bus

interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up

timer, and state-configurable timer, one comparator, function-configurable I/O ports

through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O

pins.

2. Features and benefits

 System:

 ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz with

single-cycle multiplier and fast single-cycle I/O port.

 ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).

 System tick timer.

 Serial Wire Debug (SWD) and JTAG boundary scan modes supported.

 Micro Trace Buffer (MTB) supported.

 Memory:

 Up to 16 kB on-chip flash programming memory with 64 Byte page write and erase.

 Up to 4 kB SRAM.

 ROM API support:

 Boot loader.

 USART drivers.

 I2C drivers.

 Power profiles.

 Flash In-Application Programming (IAP) and In-System Programming (ISP).

 Digital peripherals:

 High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 18

General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,

programmable open-drain mode, input inverter, and glitch filter.

 High-current source output driver (20 mA) on four pins.

 High-current sink driver (20 mA) on two true open-drain pins.

 GPIO interrupt generation capability with boolean pattern-matching feature on eight

GPIO inputs.

 Switch matrix for flexible configuration of each I/O pin function.

LPC81xM

32-bit ARM Cortex-M0+ microcontroller; up to 16 kB flash and

4 kB SRAM

Rev. 4.3 — 22 April 2014 Product data sheet

Summary of content (76 pages)

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LPC81xM 32-bit ARM Cortex-M0+ microcontroller; up to 16 kB flash and 4 kB SRAM Rev. 4.3 — 22 April 2014 Product data sheet 1. General description The LPC81xM are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 30 MHz. The LPC81xM support up to 16 kB of flash memory and 4 kB of SRAM.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller          State Configurable Timer/PWM (SCTimer/PWM) with input and output functions (including capture and match) assigned to pins through the switch matrix.  Multiple-channel multi-rate timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates.  Self Wake-up Timer (WKT) clocked from either the IRC or a low-power, low-frequency internal oscillator.  CRC engine.  Windowed Watchdog timer (WWDT).
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 4. Ordering information Table 1. Ordering information Type number Package LPC810M021FN8 Name Description Version DIP8 plastic dual in-line package; 8 leads (300 mil) SOT097-2 LPC811M001JDH16 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 LPC812M101JDH16 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 5. Marking The LPC81xM devices typically have the following top-side marking: LPC81x xxxxx xxxxxxxx xxYWWxR[x] The last two letters in the last line (field ‘xR’) identify the boot code version and device revision. Table 3. Device revision table Revision identifier (xR) Revision description ‘1A’ Initial device revision with boot code version 13.1 ‘2A’ Device revision with boot code version 13.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 6. Block diagram /3& [0 6:&/. 6:' [ 3,2 7(67 '(%8* ,17(5)$&( +,*+ 63((' *3,2 $50 &257(; 0 3,1 ,17(558376 3$77(51 0$7&+ )/$6+ N% VODYH &7287B> @ 6&7,0(5 3:0 &7,1B> @ 65$0 N% VODYH 520 VODYH $+% /,7( %86 VODYH VODYH &5& $+% 72 $3% %5,'*( 7;' 576 ::'7 5;' &76 6&/. 86$57 ,2&21 7;' 576 [ 6:,7&+ 0$75,; 5;' &76 6&/. 86$57 08/7, 5$7( 7,0(5 7;' 576 5;' &76 6&/. 86$57 6&.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 7. Pinning information 7.1 Pinning 5(6(7 3,2 B 3,2 B $&03B, 7'2 3,2 B :$.(83 7567 966 6:&/. 3,2 B 7&. 9'' 6:',2 3,2 B 706 3,2 B $&03B, &/.,1 7', ',3 DDD Fig 2. Pin configuration DIP8 package (LPC810M021JN8) 3,2 B 3,2 B $&03B, 7'2 3,2 B 3,2 B 9''&03 5(6(7 3,2 B 3,2 B 3,2 B :$.(83 7567 6:&/. 3,2 B 7&.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 3,2 B 3,2 B 3,2 B 3,2 B $&03B, 7'2 3,2 B 3,2 B 9''&03 5(6(7 3,2 B 3,2 B 3,2 B :$.(83 7567 6:&/. 3,2 B 7&. 966 9'' 6:',2 3,2 B 706 3,2 B ;7$/,1 3,2 B 3,2 B ;7$/287 3,2 B 3,2 B $&03B, &/.,1 7', 76623 3,2 B 3,2 B DDD Fig 5.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 7.2 Pin description The pin description consists of two parts showing pin functions that are fixed to a certain package pin (see Table 4) and showing pin functions that can be assigned to any pin on the package through the switch matrix (see Table 5). The pin description table in Table 4 shows the pin functions that are fixed to specific pins on each package.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Pin description table (fixed pins) SWCLK/PIO0_3/ TCK PIO0_4/WAKEUP/ TRST 6 5 XSON16 DIP8 SWDIO/PIO0_2/TMS 7 Type Reset Description state TSSOP16 Symbol SO20/ TSSOP20 Table 4. 6 6 4 5 4 5 4 [1] [2] 3 [2] 2 [6] I/O I; PU SWDIO — Serial Wire Debug I/O. SWDIO is enabled by default on this pin. In boundary scan mode: TMS (Test Mode Select). I/O - PIO0_2 — General purpose digital input/output pin.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Pin description table (fixed pins) XSON16 DIP8 PIO0_12 Type Reset Description state TSSOP16 Symbol SO20/ TSSOP20 Table 4. 3 2 2 - [1] [2] I/O I; PU PIO0_12 — General purpose digital input/output pin. ISP entry pin on the SO20/TSSOP20/TSSOP16/XSON16 packages starting with chip version 4C (see Table 6). A LOW level on this pin during reset starts the ISP command handler.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 5. Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix) Function name Type Description U0_SCLK I/O Serial clock input/output for USART0 in synchronous mode. U1_TXD O Transmitter output for USART1. U1_RXD I Receiver input for USART1. U1_RTS O Request To Send output for USART1. U1_CTS I Clear To Send input for USART1. U1_SCLK I/O Serial clock input/output for USART1 in synchronous mode.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 6. LPC81XM Product data sheet Pin location in ISP mode ISP entry pin USART RXD USART TXD Marking Boot loader version Package PIO0_1 PIO0_0 PIO0_4 1A v 13.1 TSSOP20; SO20; TSSOP16; DIP8; XSON16 PIO0_1 PIO0_0 PIO0_4 2A v 13.2 TSSOP20; SO20; TSSOP16; DIP8; XSON16 PIO0_1 PIO0_0 PIO0_4 4C and later v 13.4 and later DIP8 PIO0_12 PIO0_0 PIO0_4 4C and later v 13.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8. Functional description 8.1 ARM Cortex-M0+ core The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz using a two-stage pipeline. Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two watchpoints. The ARM Cortex-M0+ core supports a single-cycle I/O enabled port for fast GPIO access. The core includes a single-cycle multiplier and a system tick timer. 8.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Up to eight pins, regardless of the selected function, can be programmed to generate an interrupt on a level, a rising or falling edge, or both. The interrupt generating pins can be selected from all digital or mixed digital/analog pins. The pin interrupt/pattern match block controls the edge or level detection mechanism. 8.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller $3% SHULSKHUDOV *% /3& [0 [ UHVHUYHG [)))) )))) UHVHUYHG [( SULYDWH SHULSKHUDO EXV [ [( 86$57 UHVHUYHG *3,2 86$57 UHVHUYHG 63, 63, UHVHUYHG , & UHVHUYHG 6<6&21 ,2&21 IODVK FRQWUROOHU UHVHUYHG UHVHUYHG UHVHUYHG [ ))) [ UHVHUYHG [ ))) [ & UHVHUYHG DQDORJ FRPSDUDWR
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller • Program the input glitch filter with different filter constants using one of the IOCON divided clock signals (IOCONCLKCDIV, see Figure 10 “LPC81xM clock generation”). You can also bypass the glitch filter. • Invert the input signal. • Hysteresis can be enabled or disabled. • For pins PIO0_10 and PIO0_11, select the I2C-mode and output driver for standard digital operation, for I2C standard and fast modes, or for I2C Fast mode+.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 9'' 9'' RSHQ GUDLQ HQDEOH SLQ FRQILJXUHG DV GLJLWDO RXWSXW GULYHU VWURQJ SXOO XS RXWSXW HQDEOH (6' GDWD RXWSXW 3,1 VWURQJ SXOO GRZQ (6' 966 9'' ZHDN SXOO XS SXOO XS HQDEOH ZHDN SXOO GRZQ UHSHDWHU PRGH HQDEOH SLQ FRQILJXUHG DV GLJLWDO LQSXW SXOO GRZQ HQDEOH GDWD LQSXW 352*5$00$%/( */,7&+ ),/7(5 VHOHFW GDWD LQYHUWHU VHOHFW JOLWFK ILOWHU VHOHFW DQDORJ LQSXW SLQ FRQILJXUHG DV DQDORJ LQSXW DQDORJ LQSXW DDD Fig 8.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller • An entire port value can be written in one instruction. • Mask, set, and clear operations are supported for the entire port. All GPIO port pins are fixed-pin functions that are enabled or disabled on the pins by the switch matrix. Therefore each GPIO port pin is assigned to one specific pin and cannot be moved to another pin.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller – The pattern match engine does not facilitate wake-up. 8.12 USART0/1/2 Remark: USART0 and USART1 are available on all LPC800 parts. USART2 is available on parts LPC812M101JDH16 and LPC812M101JDH20 only. All USART functions are movable functions and are assigned to pins through the switch matrix. 8.12.1 Features • Maximum bit rates of 1.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller • Data frames of 1 to 16 bits supported directly. Larger frames supported by software. • Master and slave operation. • Data can be transmitted to a slave without the need to read incoming data. This can be useful while setting up an SPI memory. • Control information can optionally be written along with data. This allows very versatile operation, including “any length” frames.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller All inputs and outputs of the SCTimer/PWM are movable functions and are assigned to pins through the switch matrix. 8.15.1 Features • • • • • Two 16-bit counters or one 32-bit counter. Counters clocked by bus clock or selected input. Up counters or up-down counters. State variable allows sequencing across multiple counter cycles.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • • • • Incorrect feed sequence causes reset or interrupt if enabled. Flag to indicate watchdog reset. Programmable 24-bit timer with internal prescaler.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 9'' &203$5$725 $1$/2* %/2&. &203$5$725 ',*,7$/ %/2&. 9''&03 FRPSDUDWRU OHYHO $&03B2 V\QF HGJH GHWHFW FRPSDUDWRU HGJH 19,& LQWHUQDO YROWDJH UHIHUHQFH $&03B,> @ DDD Fig 9. Comparator block diagram 8.19.1 Features • Selectable 0 mV, 10 mV ( 5 mV), and 20 mV ( 10 mV), 40 mV ( 20 mV) input hysteresis.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.20 Clocking and power control 6<6&21 PDLQ FORFN &/2&. ',9,'(5 6<6$+%&/.',9 $+% FORFN FRUH V\VWHP DOZD\V RQ V\VWHP FORFN 6<6$+%&/.&75/> @ V\VWHP FORFN HQDEOH &/2&. ',9,'(5 8$57&/.',9 )5$&7,21$/ 5$7( *(1(5$725 PHPRULHV DQG SHULSKHUDOV SHULSKHUDO FORFNV 86$57 86$57 86$57 ,5& RVFLOODWRU &/2&. ',9,'(5 ,2&21&/.',9 ,2&21 JOLWFK ILOWHU ZDWFKGRJ RVFLOODWRU 0$,1&/.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Each oscillator, except the low-frequency oscillator, can be used for more than one purpose as required in a particular application. Following reset, the LPC81xM will operate from the IRC until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. See Figure 10 for an overview of the LPC81xM clock generation. 8.20.1.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time is nominally 100 s. 8.20.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 8.20.6.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller When entering Deep power-down mode, an external pull-up resistor is required on the WAKEUP pin to hold it HIGH. Pull the RESET pin HIGH to prevent it from floating while in Deep power-down mode. 8.21 System control 8.21.1 Reset Reset has four sources on the LPC81xM: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.21.3 Code security (Code Read Protection - CRP) CRP provides different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. Programming a specific pattern into a dedicated flash location invokes CRP. IAP commands are not affected by the CRP. In addition, ISP entry via the ISP entry pin can be disabled without enabling CRP.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 8.22 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0+. Serial wire debug functions are supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0+ is configured to support up to four breakpoints and two watch points. The Micro Trace Buffer is implemented on the LPC81xM. The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM SWD debug (RESET = HIGH).
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 9. Limiting values Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit [2] 0.5 +4.6 V 5 V tolerant I/O pins; VDD  1.8 V [3] 0.5 +5.5 V 5 V tolerant open-drain pins PIO0_10 and PIO0_11 [4] 0.5 +5.5 V 3 V tolerant I/O pin PIO0_6 [5] 0.5 +3.6 V [6] 0.5 4.6 V 0.5 +2.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 10. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb +  P D  R th  j – a   (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 11. Static characteristics Table 9. Static characteristics Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter VDD supply voltage (core and external rail) IDD supply current Conditions Min Typ[1] Max Unit 1.8 3.3 3.6 V Active mode; code while(1){} executed from flash; system clock = 12 MHz; default mode; VDD = 3.3 V [2][3][4][5] - 1.4 - mA system clock = 12 MHz; low-current mode; VDD = 3.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 9. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Standard port pins configured as digital pins, RESET; see Figure 13 IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10 nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 9. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol VI Parameter Conditions input voltage VDD  1.8 V [11] Min Typ[1] Max Unit 0 - 5.0 V [12] VDD = 0 V 0 - 3.6 V output active 0 - VDD V HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage 0.4 - - V VOH HIGH-level output voltage 2.5 V  VDD  3.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 9. Static characteristics …continued Tamb = 40 C to +105 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Oscillator input pins (PIO0_8 and PIO0_9) Vi(xtal) crystal input voltage 0.5 1.8 1.95 V Vo(xtal) crystal output voltage 0.5 1.8 1.95 V [1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 11.1 Power consumption Power measurements in Active, Sleep, Deep-sleep,and Power-down modes were performed under the following conditions: • Configure all pins as GPIO with pull-up resistor disabled in the IOCON block. • Configure GPIO pins as outputs using the GPIO DIR register. • Write 1 to the GPIO CLR register to drive the outputs LOW.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller DDD ,'' P$ 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] WHPSHUDWXUH & Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz - 6 MHz: IRC enabled; PLL disabled.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller DDD ,'' P$ 0+] 0+] 0+] 0+] 0+] 0+] 0+] 0+] WHPSHUDWXUH & Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz - 6 MHz: IRC enabled; PLL disabled.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller DDD ,'' ,'' ȝ$ 9 9 9 WHPSHUDWXUH & Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). Fig 18.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 11.2 CoreMark data DDD ,'' ,'' P$ 'HIDXOW &38 HIILFLHQF\ /RZ FXUUHQW V\VWHP FORFN IUHTXHQF\ 0+] Conditions: VDD = 3.3 V; Tamb = 25 C; active mode; all peripherals except one UART and the SCT disabled in the SYSAHBCLKCTRL register; system clock derived from the IRC; system oscillator disabled; internal pull-up resistors enabled; BOD disabled. Measured with Keil uVision v.4.7. Fig 20.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 11.3 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at Tamb = 25 C.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 11.4 Electrical pin characteristics DDD 92+ 92+ P$ ¡& 9 & Y & 9 ¡& 9 & 9 ¡& 9 & 9 ¡& 9 ¡& 9 & Y & 9 ¡& 9 & 9 ¡& 9 & 9 ¡& 9 ,2+ P$ Conditions: VDD = 3.3 V and VDD = 1.8 V; on pins PIO0_2, PIO0_3, PIO0_7, PIO0_12, PIO0_13. Fig 22.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller DDD ¡& 9 & 9 & 9 ¡& 9 & 9 ¡& 9 & 9 ¡& 9 & 9 ¡& 9 & 9 ¡& 9 & 9 ¡& 9 & 9 ¡& 9 ,2/ ,2/ P$ 92/ 9 Conditions: VDD = 3.3 V and VDD = 1.8 V; standard port pins and high-drive pins PIO0_2, PIO0_3, PIO0_7, PIO0_12, PIO0_13. Fig 24.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller DDD ,SX ,SX P$ 9'' 9 ¡& & & ¡& & ¡& & ¡& & ¡& & ¡& & ¡& & ¡& & ¡& & ¡& 9'' 9 9, 9 Conditions: VDD = 3.3 V and VDD = 1.8 V; standard port pins. Fig 26.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 12. Dynamic characteristics 12.1 Flash memory Table 11. Flash characteristics Tamb = 40 C to +105 C. Based on JEDEC NVM qualification. Failure rate < 10 ppm for parts as specified below.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 12.3 Internal oscillators Table 13. Dynamic characteristics: IRC Tamb = 40 C to +105 C; 2.7 V  VDD  3.6 V[1]. Symbol Parameter Conditions Min Typ[2] Max Unit fosc(RC) internal RC oscillator frequency Tamb = 40 C to +105 C 11.82 12 12.18 MHz [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 12.4 I/O pins Table 15. Dynamic characteristics: I/O pins[1] Tamb = 40 C to +105 C; 3.0 V  VDD  3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.0 ns [1] Applies to standard port pins and RESET pin. 12.5 I2C-bus Table 16. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +105 C.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller [3] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. [5] Cb = total capacitance of one bus line in pF.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 12.6 SPI interfaces The maximum data bit rate is 30 Mbit/s in master mode and 25 Mbit/s in slave mode. Remark: SPI functions can be assigned to all digital pins. The characteristics are valid for all digital pins except the open-drain pins PIO0_10 and PIO0_11. Table 17. SPI dynamic characteristics Tamb = 40 C to 105 C; 1.8 V  VDD  3.6 V.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 7F\ FON 6&. &32/ 6&. &32/ WY 4 WK 4 '$7$ 9$/,' 026, '$7$ 9$/,' W'6 '$7$ 9$/,' 0,62 W'+ '$7$ 9$/,' WY 4 026, '$7$ 9$/,' WK 4 '$7$ 9$/,' W'+ W'6 0,62 '$7$ 9$/,' &3+$ &3+$ '$7$ 9$/,' DDD Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. Fig 31. SPI master timing LPC81XM Product data sheet All information provided in this document is subject to legal disclaimers.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 7F\ FON 6&. &32/ 6&. &32/ W'6 026, '$7$ 9$/,' W'+ '$7$ 9$/,' WY 4 0,62 WK 4 '$7$ 9$/,' W'6 026, '$7$ 9$/,' W'+ '$7$ 9$/,' WY 4 0,62 '$7$ 9$/,' &3+$ '$7$ 9$/,' WK 4 &3+$ '$7$ 9$/,' DDD Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. Fig 32. SPI slave timing LPC81XM Product data sheet All information provided in this document is subject to legal disclaimers.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 12.7 USART interface The maximum USART bit rate is 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in synchronous mode slave and master mode. Remark: USART functions can be assigned to all digital pins. The characteristics are valid for all digital pins except the open-drain pins PIO0_10 and PIO0_11. Table 18. USART dynamic characteristics Tamb = 40 C to 105 C; 1.8 V  VDD  3.6 V.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 13. Analog characteristics 13.1 BOD Table 19. BOD static characteristics[1] Tamb = 40 C to +105 C. Typ[2] Unit assertion 2.3 V de-assertion 2.4 V assertion 2.6 V de-assertion 2.7 V assertion 2.8 V de-assertion 2.9 V assertion 2.1 V de-assertion 2.2 V assertion 2.4 V de-assertion 2.5 V assertion 2.6 V de-assertion 2.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller [3] Typical values are derived from nominal simulation (VDD = 3.3 V; Tamb = 27 C; nominal process models). Maximum values are derived from worst case simulation (VDD = 2.6 V; Tamb = 105 C; slow process models). [4] Maximum and minimum values are measured on samples from the corners of the process matrix lot. DDD 92 92 P9 WHPSHUDWXUH & VDD = 3.3 V Fig 34.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 21. Comparator characteristics …continued VDD = 3.0 V and Tamb = 27 C unless noted otherwise. Symbol Parameter Conditions tPD propagation delay HIGH to LOW; VDD = 3.0 V; propagation delay tPD Min Typ Max - 109 121 Unit VIC = 0.1 V; 50 mV overdrive input [1] VIC = 0.1 V; rail-to-rail input [1] - 155 164 ns VIC = 1.5 V; 50 mV overdrive input [1] - 95 105 ns VIC = 1.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 23. Comparator voltage ladder reference static characteristics VDD = 3.3 V; Tamb = 40 C to + 105C. Symbol Parameter Conditions Min Typ Max[1] Unit EV(O) output voltage error Internal VDD supply - 0 0 % decimal code = 08 - 0 0.4 % decimal code = 16 - 0.2 0.2 % decimal code = 24 - 0.2 0.2 % decimal code = 30 - 0.1 0.1 % decimal code = 31 - 0.1 0.1 % - 0 0 % decimal code = 08 - 0.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 14. Application information 14.1 Typical wake-up times Table 24. Typical wake-up times (3.3 V, Temp = 25 °C) Power modes Sleep mode (12 Deep-sleep MHz)[1][2] mode[1][3] Power-down mode[1][3] Deep Power-down mode[4] VDD current Wake-up time 0.7 mA 2.6 s 150 A 4 s 0.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller RS). Capacitance CP in Figure 36 represents the parallel package capacitance and should not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal manufacturer (see Table 25). /3& / ;7$/,1 ;7$/287 &/ &3 ;7$/ 56 &; &; DDD Fig 36. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 25.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 14.3 XTAL Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1,Cx2, and Cx3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 15. Package outline DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-2 ME seating plane D A2 A A1 L c e Z w b1 (e1) b MH b2 8 5 pin 1 index E 1 4 0 2.5 5 mm scale Dimensions (inch dimensions are derived from the original dimensions) Unit(1) mm max nom min A A1 4.2 A2 b 3.43 1.73 b1 b2 c D(1) E(1) 0.53 1.07 0.38 9.8 6.48 e e1 L ME MH 0.51 1.14 0.38 0.89 0.20 9.2 6.20 Z(1) 1.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 20 11 Q A2 A (A 3) A1 pin 1 index θ Lp L 10 1 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller XSON16: plastic extremely thin small outline package; no leads; 16 terminals; body 2.5 x 3.2 x 0.5 mm SOT1341-1 X D B A E A A1 c detail X terminal 1 index area e1 terminal 1 index area C e v w b 1 8 C A B C y1 C y L1 k L 16 9 0 1 2 3 mm scale Dimensions (mm are the original dimensions) Unit(1) mm max nom min A 0.5 A1 b c 0.05 0.25 0.152 0.20 0.00 0.15 0.050 D E 3.3 3.2 3.1 2.6 2.5 2.4 e e1 0.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 16. Soldering Footprint information for reflow soldering of TSSOP16 package SOT403-1 Hx Gx P2 (0.125) Hy Gy (0.125) By Ay C D2 (4x) D1 P1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0.650 0.750 7.200 4.500 1.350 0.400 0.600 5.600 5.300 5.800 7.450 sot403-1_fr Fig 42.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 13.40 0.60 (20×) 1.50 8.00 11.00 11.40 1.27 (18×) solder lands occupied area placement accuracy ± 0.25 Dimensions in mm sot163-1_fr Fig 43. Reflow soldering of the SO20 package LPC81XM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.3 — 22 April 2014 © NXP Semiconductors N.V. 2014. All rights reserved.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Footprint information for reflow soldering of TSSOP20 package SOT360-1 Hx Gx P2 (0.125) Hy Gy (0.125) By Ay C D2 (4x) D1 P1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0.650 0.750 7.200 4.500 1.350 0.400 0.600 6.900 5.300 7.300 7.450 sot360-1_fr Fig 44.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller )RRWSULQW LQIRUPDWLRQ IRU UHIORZ VROGHULQJ RI ;621 SDFNDJH 627 RFFXSLHG DUHD VROGHU UHVLVW VROGHU ODQGV VROGHU SDVWH 'LPHQVLRQV LQ PP ,VVXH GDWH VRW BIU Fig 45. Reflow soldering of the XSON16 package LPC81XM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 17. Abbreviations Table 27. Abbreviations Acronym Description AHB Advanced High-performance Bus APB Advanced Peripheral Bus BOD BrownOut Detection GPIO General-Purpose Input/Output PLL Phase-Locked Loop RC Resistor-Capacitor SPI Serial Peripheral Interface SMBus System Management Bus TEM Transverse ElectroMagnetic UART Universal Asynchronous Receiver/Transmitter 18.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 19. Revision history Table 28. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC81XM v.4.3 20140422 Product data sheet - Modifications: • • Section 8.20.2 “Clock input” updated for clarity. • • • • • • Name “SCT” changed to “SCTimer/PWM” for clarity. • Table 21: Added Vref(cmp) spec for PIO0_6/VDDCMP. LPC81XM v.4.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Table 28. Revision history …continued Document ID LPC81XM v.2 Modifications: LPC81XM v.1 LPC81XM Product data sheet Release date Data sheet status Change notice Supersedes • • Editorial updates (temperature sensor removed). • IDD in Deep power-down mode added for condition Low-power oscillator on/WKT wake-up enabled. See Table 10. • • • • • • • • • Table note 3 updated for Table 4 “Pin description table (fixed pins)”.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 20. Legal information 20.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 22. Contents 1 2 3 4 4.1 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.5.1 8.5.2 8.6 8.7 8.8 8.8.1 8.9 8.10 8.10.1 8.11 8.11.1 8.12 8.12.1 8.13 8.13.1 8.14 8.14.1 8.15 8.15.1 8.16 8.16.1 8.17 8.17.1 8.18 8.18.1 8.19 8.19.1 8.20 8.20.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 16 17 18 19 20 20.1 20.2 20.3 20.4 21 22 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . .