Datasheet

LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.3 — 22 April 2014 14 of 76
NXP Semiconductors
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
Up to eight pins, regardless of the selected function, can be programmed to generate an
interrupt on a level, a rising or falling edge, or both. The interrupt generating pins can be
selected from all digital or mixed digital/analog pins. The pin interrupt/pattern match block
controls the edge or level detection mechanism.
8.6 System tick timer
The ARM Cortex-M0+ includes a 24-bit system tick timer (SysTick) that is intended to
generate a dedicated SysTick exception at a fixed time interval (typically 10 ms).
8.7 Memory map
The LPC81xM incorporates several distinct memory regions. Figure 7 shows the overall
map of the entire address space from the user program viewpoint following reset. The
interrupt vector area supports address remapping.
The ARM private peripheral bus includes the ARM core registers for controlling the NVIC,
the system tick timer (SysTick), and the reduced power modes.