Datasheet

LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.3 — 22 April 2014 20 of 76
NXP Semiconductors
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
• Data frames of 1 to 16 bits supported directly. Larger frames supported by software.
• Master and slave operation.
• Data can be transmitted to a slave without the need to read incoming data. This can
be useful while setting up an SPI memory.
• Control information can optionally be written along with data. This allows very
versatile operation, including “any length” frames.
• One Slave Select input/output with selectable polarity and flexible usage.
Remark: Texas Instruments SSI and National Microwire modes are not supported.
8.14 I2C-bus interface
The I
2
C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
2
C is a multi-master bus and can be
controlled by more than one bus master connected to it.
The I2C-bus functions are movable functions and can be assigned through the switch
matrix to any pin. However, only the true open-drain PIO0_10 and PIO0_11 provide the
electrical characteristics to support the full I2C-bus specification (see Ref. 1
).
8.14.1 Features
• Supports standard and fast mode with data rates of up to 400 kbit/s.
• Independent Master, Slave, and Monitor functions.
• Supports both Multi-master and Multi-master with Slave functions.
• Multiple I
2
C slave addresses supported in hardware.
• One slave address can be selectively qualified with a bit mask or an address range in
order to respond to multiple I
2
C bus addresses.
• 10-bit addressing supported with software assist.
• Supports SMBus.
• Supported by on-chip ROM API.
• If the I2C functions are connected to the true open-drain pins (PIO0_10 and
PIO0_11), the I2C supports the full I2C-bus specification:
– Fail-safe operation: When the power to an I
2
C-bus device is switched off, the SDA
and SCL pins connected to the I
2
C-bus are floating and do not disturb the bus.
– Supports Fast-mode Plus with bit rates up to 1 Mbit/s.
8.15 State-Configurable Timer/PWM (SCTimer/PWM)
The state configurable timer (SCTimer/PWM or SCT) can perform basic 16-bit and 32-bit
timer/counter functions with match outputs and external and internal capture inputs. In
addition, the SCTimer/PWM can employ up to two different programmable states, which
can change under the control of events, to provide complex timing patterns.