Datasheet
LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.3 — 22 April 2014 28 of 76
NXP Semiconductors
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
When entering Deep power-down mode, an external pull-up resistor is required on the
WAKEUP pin to hold it HIGH. Pull the RESET
pin HIGH to prevent it from floating while in
Deep power-down mode.
8.21 System control
8.21.1 Reset
Reset has four sources on the LPC81xM: the RESET pin, the Watchdog reset, power-on
reset (POR), and the BrownOut Detection (BOD) circuit. The RESET
pin is a Schmitt
trigger input pin. Assertion of chip reset by any source, once the operating voltage attains
a usable level, starts the IRC and initializes the flash controller.
A LOW-going pulse as short as 50 ns resets the part.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
In Deep power-down mode, an external pull-up resistor is required on the RESET
pin.
8.21.2 Brownout detection
The LPC81xM includes up to four levels for monitoring the voltage on the V
DD
pin. If this
voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the
NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC
to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a
dedicated status register. Four threshold levels can be selected to cause a forced reset of
the chip.
Fig 11. Reset pad configuration
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