Datasheet

LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.3 — 22 April 2014 38 of 76
NXP Semiconductors
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
Conditions: V
DD
= 3.3 V; active mode entered executing code while(1){} from flash; all
peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral
clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode.
1 MHz - 6 MHz: IRC enabled; PLL disabled.
12 MHz: IRC enabled; PLL disabled.
24 MHz: IRC enabled; PLL enabled.
30 MHz: IRC disabled; SYSOSC enabled; PLL enabled.
Fig 15. Active mode: Typical supply current I
DD
versus temperature
DDD
     






WHPSHUDWXUH&
,
''''
,
''
P$P$P$
0+]0+]0+]
0+]0+]0+]
0+]0+]0+]
0+]0+]0+]
0+]0+]0+]
0+]0+]0+]
0+]0+]0+]
0+]0+]0+]