Datasheet

LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.3 — 22 April 2014 41 of 76
NXP Semiconductors
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
11.2 CoreMark data
Conditions: V
DD
= 3.3 V; T
amb
= 25 C; active mode; all peripherals except one UART and the SCT
disabled in the SYSAHBCLKCTRL register; system clock derived from the IRC; system oscillator
disabled; internal pull-up resistors enabled; BOD disabled. Measured with Keil uVision v.4.7.
Fig 20. Active mode: CoreMark power consumption I
DD
Conditions: V
DD
= 3.3 V; active mode; all peripherals except one UART and the SCT disabled in
the SYSAHBCLKCTRL register; internal pull-up resistors enabled; BOD disabled. Measured with
Keil uVision v.4.7.
Fig 21. CoreMark score
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