Datasheet

LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.3 — 22 April 2014 50 of 76
NXP Semiconductors
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
12.6 SPI interfaces
The maximum data bit rate is 30 Mbit/s in master mode and 25 Mbit/s in slave mode.
Remark: SPI functions can be assigned to all digital pins. The characteristics are valid for
all digital pins except the open-drain pins PIO0_10 and PIO0_11.
[1] Capacitance on pin SPIn_SCK C
SCK
< 5 pF.
[2] T
cy(clk)
= DIVVAL/CCLK with CCLK = system clock frequency. DIVVAL is the SPI clock divider. See the
LPC800 User manual UM10601.
Table 17. SPI dynamic characteristics
T
amb
=  40  C to 105  C; 1.8 V  V
DD
 3.6 V. Simulated parameters sampled at the 50 % level of
the rising or falling edge; values guaranteed by design.
Symbol Parameter Conditions Min Max Unit
SPI master
[1]
T
cy(clk)
clock cycle time
[2]
33 - ns
t
DS
data set-up time 0 - ns
t
DH
data hold time 16 - ns
t
v(Q)
data output valid time C
L
= 10 pF - 0.5 ns
t
h(Q)
data output hold time C
L
= 10 pF 0.5 - ns
SPI slave
T
cy(clk)
40 ns
t
DS
data set-up time 0 - ns
t
DH
data hold time 16 - ns
t
v(Q)
data output valid time C
L
= 10 pF - 10 ns
t
h(Q)
data output hold time C
L
= 10 pF 10 - ns