Datasheet

LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 4.3 — 22 April 2014 72 of 76
NXP Semiconductors
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
• Editorial updates (temperature sensor removed).
• CoreMark data added. See Figure 19 “Active mode: CoreMark power consumption
IDD” and Figure 20 “CoreMark score”.
• I
DD
in Deep power-down mode added for condition Low-power oscillator on/WKT
wake-up enabled. See Table 10.
• Table note 3 updated for Table 4 “Pin description table (fixed pins)”.
• Conditions for t
er
and t
prog
updated in Table 12 “Flash characteristics”.
• Section 13.3 “Internal voltage reference” added.
• Typical timing data added for SPI. See Section 12.6.
• Typical timing data added for USART in synchronous mode. See Section 12.7.
• BOD characterization added. See Section 13.1.
• IRC characterization added. See Section 12.3.
• Internal voltage reference characteristics added. See Section 13.3.
• Data sheet status changed to Preliminary data sheet.
LPC81XM v.2 20130128 Objective data sheet - LPC81XM v.1
Modifications:
• MTB memory space changed to 1 kB in Figure 6.
• Electrical pin characteristics added in Table 10.
• Figure 11 “Connecting the SWD pins to a standard SWD connector” added.
• Peripheral power consumption added in Table 11.
• Table 7 updated.
• MRT implementation changed to 31-bit timer.
• Power consumption data in active and sleep mode with IRC added. See Figure 13 to
Figure 15.
• Power consumption (parameter I
DD
) in active and sleep mode for low-power mode at
12 MHz corrected in Table 10.
• Power consumption (parameter I
DD
) in active and sleep mode at 24 MHz added in
Table 10.
• Maximum USART speed in synchronous mode changed to 10 Mbit/s.
• Section 5 “Marking” added.
LPC81XM v.1 20121112 Objective data sheet - -
Table 28. Revision history
…continued
Document ID Release date Data sheet status Change notice Supersedes