Datasheet

Product data sheet Rev. 4.3 — 22 April 2014 21 of 76

NXP Semiconductors

LPC81xM

32-bit ARM Cortex-M0+ microcontroller

All inputs and outputs of the SCTimer/PWM are movable functions and are assigned to

pins through the switch matrix.

8.15.1 Features

• Two 16-bit counters or one 32-bit counter.

• Counters clocked by bus clock or selected input.

• Up counters or up-down counters.

• State variable allows sequencing across multiple counter cycles.

• The following conditions define an event: a counter match condition, an input (or

output) condition, a combination of a match and/or and input/output condition in a

specified state, and the count direction.

• Events control outputs, interrupts, and the SCT states.

– Match register 0 can be used as an automatic limit.

– In bi-directional mode, events can be enabled based on the count direction.

– Match events can be held until another qualifying event occurs.

• Selected events can limit, halt, start, or stop a counter.

• Supports:

– 4 inputs

– 4 outputs

– 5 match/capture registers

– 6 events

– 2 states

8.16 Multi-Rate Timer (MRT)

The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each

channel can be programmed with an independent time interval, and each channel

operates independently from the other channels.

8.16.1 Features

• 31-bit interrupt timer

• Four channels independently counting down from individually set values

• Bus stall, repeat and one-shot interrupt modes

8.17 Windowed WatchDog Timer (WWDT)

The watchdog timer resets the controller if software fails to periodically service it within a

programmable time window.

8.17.1 Features

• Internally resets chip if not periodically reloaded during the programmable time-out

period.

• Optional windowed operation requires reload to occur between a minimum and

maximum time period, both programmable.