Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller HVQFN 33 (5x5) 32-Bit 30 MHz I/O number 29

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1. General description

The LPC82x are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at

CPU frequencies of up to 30 MHz. The LPC82x support up to 32 KB of flash memory and

8 KB of SRAM.

The peripheral complement of the LPC82x includes a CRC engine, four I

C-bus

interfaces, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self

wake-up timer, and state-configurable timer with PWM function (SCTimer/PWM), a DMA,

one 12-bit ADC and one analog comparator, function-configurable I/O ports through a

switch matrix, an input pattern match engine, and up to 32 general-purpose I/O pins.

For additional documentation related to the LPC82x parts, see Section 18

2. Features and benefits

 System:

 ARM Cortex-M0+ processor (revision r0p1), running at frequencies of up to

30 MHz with single-cycle multiplier and fast single-cycle I/O port.

 ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).

 System tick timer.

 AHB multilayer matrix.

 Serial Wire Debug (SWD) with four break points and two watch points. JTAG

boundary scan (BSDL) supported.

 MTB

 Memory:

 Up to 32 KB on-chip flash programming memory with 64 Byte page write and

erase. Code Read Protection (CRP) supported.

 8 KB SRAM.

 ROM API support:

 Boot loader.

 On-chip ROM APIs for ADC, SPI, I2C, USART, power configuration (power

profiles) and integer divide.

 Flash In-Application Programming (IAP) and In-System Programming (ISP).

 Digital peripherals:

 High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 32

General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,

programmable open-drain mode, input inverter, and digital filter. GPIO direction

control supports independent set/clear/toggle of individual bits.

 High-current source output driver (20 mA) on four pins.

LPC82x

32-bit ARM Cortex-M0+ microcontroller; up to 32 kB flash and

8 kB SRAM; 12-bit ADC; comparator

Rev. 0.11 — 26 August 2014 Product data sheet

Summary of content (81 pages)

PAGE 1
D D D D D R R R R R A A A A A D R R A A FT FT FT FT A A R R D D D D D R R A FT FT FT A A R R D D 32-bit ARM Cortex-M0+ microcontroller; up to 32 kB flash and 8 kB SRAM; 12-bit ADC; comparator R D D D A F FT FT A A R Product data sheet R Rev. 0.11 — 26 August 2014 FT FT FT FT FT LPC82x D FT FT A A R R D D D R A FT 1. General description D For additional documentation related to the LPC82x parts, see Section 18. 2.
PAGE 2
D D D D D R R R R R A A FT FT FT FT FT LPC82x A A A D R R FT FT FT FT 32-bit ARM Cortex-M0+ microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D  High-current sink driver (20 mA) on two true open-drain pins.  GPIO interrupt generation capability with boolean pattern-matching feature on eight GPIO inputs.  Switch matrix for flexible configuration of each I/O pin function.  CRC engine.
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D D D D D FT FT FT FT FT D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D D D R A FT D     A A A A A LPC82x 32-bit ARM Cortex-M0+ microcontroller  Power-On Reset (POR).  Brownout detect (BOD). Unique device serial number for identification. Single power supply (1.8 V to 3.6 V). Operating temperature range -40 °C to +105 °C. Available in a TSSOP20 and HVQFN33 (5x5) package.
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D D D D D A A A A A FT FT FT FT FT LPC82x D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 5. Marking R R R R R NXP Semiconductors D FT FT A A R R D 20 D D Terminal 1 index area R A FT R NXP D NXP 1 aaa-014766 Fig 1. A Terminal 1 index area TSSOP20 package marking aaa-014382 Fig 2.
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D D D D D A A A A A FT FT FT FT FT LPC82x D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 6.
PAGE 6
D D D D D FT FT FT FT FT D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D 7.1 Pinning A A A A A LPC82x 32-bit ARM Cortex-M0+ microcontroller 7.
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D D D D D A A A A A FT FT FT FT FT LPC82x D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The pin description table Table 3 shows the pin functions that are fixed to specific pins on each package. These fixed-pin functions are selectable through the switch matrix between GPIO and the comparator, ADC, SWD, RESET, and the XTAL pins.
PAGE 8
D D D D D D R R A FT FT A R A FT D R A This pin triggers a wake-up from Deep power-down mode. If you need to wake up from Deep power-down mode via an external pin, do not assign any movable function to this pin. This pin should be pulled HIGH externally before entering Deep power-down mode. A LOW-going pulse as short as 50 ns causes the chip to exit Deep power-down mode and wakes up the part. 3 [7] I; PU A ADC_11 — ADC input 11.
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D D D D D D R R A TSSOP20 HVQFN33 28 [2] 27 [2] [2] I; PU I; PU I; PU I; PU R - 29 [2] I; PU D PIO0_26 - IO PIO0_18 — General purpose port 0 input/output 18. A ADC_8 — ADC input 8. IO PIO0_19 — General purpose port 0 input/output 19. A ADC_7 — ADC input 7. IO PIO0_20 — General purpose port 0 input/output 20. A ADC_6 — ADC input 6. IO PIO0_21 — General purpose port 0 input/output 21. A ADC_5 — ADC input 5. IO PIO0_22 — General purpose port 0 input/output 22.
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D D D D D R R R R R A A FT FT FT FT FT LPC82x A A A D R R FT FT FT FT 32-bit ARM Cortex-M0+ microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. This pin is active in Deep power-down mode and includes a 20 ns glitch filter (active in all power modes).
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D D D D D D R R FT F D I Pin input 2 to the SCT input multiplexer. SCT_PIN3 I Pin input 3 to the SCT input multiplexer. SCT_OUT0 O SCT output 0. SCT_OUT1 O SCT output 1. SCT_OUT2 O SCT output 2. SCT_OUT3 O SCT output 3. SCT_OUT4 O SCT output 4. SCT_OUT5 O SCT output 5. I2C1_SDA I/O I2C1-bus data input/output. I2C1_SCL I/O I2C1-bus clock input/output. I2C2_SDA I/O I2C2-bus data input/output. I2C2_SCL I/O I2C2-bus clock input/output.
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D D D D D FT FT FT FT FT D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D 8.1 ARM Cortex-M0+ core A A A A A LPC82x 32-bit ARM Cortex-M0+ microcontroller 8. Functional description R R R R R NXP Semiconductors D D R A FT The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz using a two-stage pipeline. The core revision is r0p1. D 8.
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D D D D D D R R FT D R I2C2 27 USART2 26 USART1 25 USART0 24 reserved 23 SPI1 22 SPI0 21 I2C1 20 I2C0 D 28 R 0x4007 4000 A 0x4007 0000 0x4006 C000 0x4006 8000 0x4006 4000 0x4006 0000 0x4005 C000 0x4005 8000 0x4005 4000 0x4005 0000 15 reserved 14 reserved 13 reserved 12 reserved 11 input mux 10 DMA TRIGMUX 9 analog comparator 8 PMU 0x4002 0000 7 12-bit ADC 0x4001 C000 6 reserved 0x4001 8000 5 reserved 0x4001 4000 4 reserved 0x4001 0000 0x1001 2000
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D D D D D D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D Supports 32 vectored interrupts. A A A A R R D D D Controls system exceptions and peripheral interrupts. FT FT FT FT FT Tightly coupled interrupt controller provides low interrupt latency.
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D D D D D A A A A A FT FT FT FT FT LPC82x D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D • Digital input: Repeater mode enabled/disabled. • Digital input: Programmable input digital filter selectable on all pins. • Analog input: Selected through the switch matrix.
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D D D D D A A A A A FT FT FT FT FT LPC82x D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R A FT FT A A R R D D Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation. F FT FT A A R R D D D 8.
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D D D D D R R R R R A A FT FT FT FT FT LPC82x A A A D R R FT FT FT FT 32-bit ARM Cortex-M0+ microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F D FT FT A A R R D • Pin interrupt pattern match engine D FT FT A A R R D D – Pin interrupts can wake up the LPC82x from sleep mode, deep-sleep mode, and power-down mode.
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D D D D D R R R R R A A FT FT FT FT FT LPC82x A A A D R R FT FT FT FT 32-bit ARM Cortex-M0+ microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D FT FT R A Built-in Baud Rate Generator. A fractional rate divider is shared among all UARTs.
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D D D D D R R R R R A A FT FT FT FT FT LPC82x A A A D R R FT FT FT FT 32-bit ARM Cortex-M0+ microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed.
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D D D D D D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D D D R • Counter/timer features: A FT D – Each SCTimer is configurable as two 16-bit counters or one 32-bit counter. R A – Counters can be clocked by the system clock or selected input. – Configurable as up counters or up-down counters. – Configurable number of match and capture registers. Up to eight match and capture registers total.
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D D D D D A A A A A FT FT FT FT FT LPC82x D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each channel can be programmed with an independent time interval, and each channel operates independently from the other channels. F FT FT A A R R D D D 8.
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D D D D D A A A A A FT FT FT FT FT LPC82x D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D • The WKT can be used for waking up the part from any reduced power mode, including Deep power-down mode, or for general-purpose timing. R R R R R NXP Semiconductors D FT FT A A R R D 8.
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D D D D D D R R D A FT R A F FT FT A A R R D D D D FT FT A A R R D D D R A (VREFP-VREFN)/2 + VREFN = VDD/2 8.21.1 Features 12-bit successive approximation analog to digital converter. 12-bit conversion rate of up to 1.2 MSamples/s. Two configurable conversion sequences with independent triggers. Optional automatic high/low threshold comparison and zero-crossing detection. Power-down mode and low-power operating mode.
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D D D D D A A A A A FT FT FT FT FT LPC82x D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 8.
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D D D D D R R R R R A A FT FT FT FT FT LPC82x A A A D R R FT FT FT FT 32-bit ARM Cortex-M0+ microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D Each oscillator, except the low-frequency oscillator, can be used for more than one purpose as required in a particular application. D FT FT A A R R D Following reset, the LPC82x will operate from the IRC until switched by software.
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D D D D D R R R R R A A FT FT FT FT FT LPC82x A A A D R R FT FT FT FT 32-bit ARM Cortex-M0+ microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock.
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D D D D D R R R R R A A FT FT FT FT FT LPC82x A A A D R R FT FT FT FT 32-bit ARM Cortex-M0+ microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D In Sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution.
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D D D D D R R R R R A A FT FT FT FT FT LPC82x A A A D R R FT FT FT FT 32-bit ARM Cortex-M0+ microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D When entering Deep power-down mode, an external pull-up resistor is required on the WAKEUP pin to hold it HIGH. Pull the RESET pin HIGH to prevent it from floating while in Deep power-down mode. D FT FT A A R R D R A FT D 8.23.
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D D D D D A A A A A FT FT FT FT FT LPC82x D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R A FT CRP provides different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. Programming a specific pattern into a dedicated flash location invokes CRP. IAP commands are not affected by the CRP.
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D D D D D A A A A A FT FT FT FT FT LPC82x D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R A FT FT A A R R D D Debug functions are integrated into the ARM Cortex-M0+. Serial wire debug functions are supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0+ is configured to support up to four breakpoints and two watch points. F FT FT A A R R D D D 8.
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D D D D D D R R FT A FT V D R A 0.5 VDD V [3][4] 0.5 +5.5 V on I2C open-drain pins PIO0_10, PIO0_11 [5] 0.5 +5.5 V 3 V tolerant I/O pin PIO0_6 [6] 0.5 +3.6 V [7][8] 0.5 +4.6 V 0.5 +2.5 V [9] [2] IDD supply current per supply pin - 100 mA ground current per ground pin - 100 mA Ilatch I/O latch-up current (0.5VDD) < VI < (1.
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D D D D D FT FT FT FT FT D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D 10. Thermal characteristics A A A A A LPC82x 32-bit ARM Cortex-M0+ microcontroller [11] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
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D D D D D D R R D A FT R A F FT FT A A R R D D D D FT FT A A R R D D D R A FT Max Unit fclk clock frequency internal CPU/system clock - - 30 MHz VDD supply voltage (core and external rail) 1.8 3.3 3.6 V Vref reference voltage on pin VREFP 2.4 - VDD V Oscillator pins Vi(xtal) crystal input voltage on pin XTALIN 0.5 1.8 1.95 V Vo(xtal) crystal output voltage on pin XTALOUT 0.5 1.8 1.
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D D D D D D R R FT R D FT FT A A R R D Unit - 1.85 - mA - 1.0 - mA - 3.95 - mA - 3.2 - mA - 1.35 - mA - 0.8 - mA - 2.55 - mA - 2.1 - mA R A FT D R A system clock = 12 MHz; default mode; VDD = 3.3 V [2][3][4] system clock = 12 MHz; low-current mode; VDD = 3.3 V [2][3][4] system clock = 30 MHz; default mode; VDD = 3.3 V [2][3][6] system clock = 30 MHz; low-current mode; VDD = 3.
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D D D D D D R R D A FT R - 1.1 - Deep power-down mode; VDD = 3.3 V; external clock input WKTCLKIN @ 10 kHz with wake-up timer enabled - 0.4 - A Deep power-down mode; VDD = 3.3 V; external clock input WKTCLKIN @ 32 kHz with wake-up timer enabled - 0.7 - A A A R FT FT A R A FT D [6] BOD disabled. [7] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks to USART, CLKOUT, and IOCON disabled in system configuration block.
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D D D D D D R R FT R D FT FT A A R R D R A FT VI = VDD; on-chip pull-down resistor disabled - 0.5 10[2] nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10[2] nA VI input voltage VDD  1.8 V; 5 V tolerant pins except PIO0_12 0 - 5 V VDD = 0 V 0 - 3.6 V output active 0 - VDD V V A HIGH-level input current R IIH D nA [4] [6] VO output voltage VIH HIGH-level input voltage 0.
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D D D D D D R R FT R 3.6 V output active 0 - VDD V V F - A R R 0 Unit D VDD = 0 V D A FT FT A A A 5.0 FT V FT D D [6] D R R - VDD  1.8 V R A D D 0 input voltage D R FT FT A A R R D D D Max [4] FT FT FT FT Typ[1] Conditions A A A A R R D D D VI Min Parameter FT FT FT FT FT Symbol A A A A A LPC82x 32-bit ARM Cortex-M0+ microcontroller Table 9.
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D D D D D D R R D A FT R F D FT FT A A R R D D D Pull-up and pull-down currents are measured across the weak internal pull-up/pull-down resistors. See Figure 12. To VSS. A FT FT A A R R D D D [8] [9] R R FT FT A A R R D D D Allowed as long as the current limit does not exceed the maximum current allowed by the device. FT FT FT FT Tri-state outputs go into tri-state mode in Deep power-down mode.
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D D D D D D R R D A FT R R FT FT A A R R A FT D R A 3.6 Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL =0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz - 6 MHz: external clock; IRC, PLL disabled. 12 MHz: IRC enabled; PLL disabled. 24 MHz: IRC enabled; PLL enabled. 30 MHz: system oscillator enabled; PLL enabled. Fig 13.
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D D D D D D R R D A FT R D FT FT A A R R D R A FT D R A 80 temperature (°C) 110 Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL =0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz - 6 MHz: external clock; IRC, PLL disabled. 12 MHz: IRC enabled; PLL disabled. 24 MHz: IRC enabled; PLL enabled.
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D D D D D D R R D A FT R D FT FT A A R R D R A FT D R A 110 1 MHz - 6 MHz: external clock; IRC, PLL disabled. 12 MHz: IRC enabled; PLL disabled. 24 MHz: IRC enabled; PLL enabled. 30 MHz: system oscillator enabled; PLL enabled. Fig 15. Sleep mode: Typical supply current IDD versus temperature for different system clock frequencies aaa-013983 VDDV= 3.6 V 3.6 3.3 V 2.7 V 2V 1.
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D D D D D A A A A A FT FT FT FT FT LPC82x D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D A F FT FT D FT FT A A R R D IDD (μA) R A A R R D D D aaa-013984 25 R R R R R NXP Semiconductors D D 20 R A FT D R 15 A VDD V 3.6 VV DD == 3.6 3.3 V 1.
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D D D D D A A A A A FT FT FT FT FT LPC82x D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R F FT FT A A A R R D D D aaa-013991 D FT FT A A R R D 3 IDD (μA) 2.5 R R R R R NXP Semiconductors R A FT D 2 D D V 3.6 DD = 3.6 V 3.3 V 2.4 V 1.8 V R A 1.5 1 0.5 0 -40 -10 20 50 80 temperature (°C) 110 WKT running with internal 10 kHz low-power oscillator. Fig 19.
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D D D D D A A A A A FT FT FT FT FT LPC82x D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R F FT FT A A A R R D D D aaa-014388 D FT FT A A R R D 3 IDD (μA) 2.5 R R R R R NXP Semiconductors R A FT D 2 D D VDD == 3.6 VDD 3.6 VV 3.3 V 2.7 V 1.8 V R A 1.5 1 0.5 0 -40 -10 20 50 80 temperature (°C) 110 WKT running with external 32 kHz clock.
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D D D D D FT FT FT FT FT D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D aaa-014006 2.5 coremark score ((iterations/s)/MHz) A A A A A LPC82x 32-bit ARM Cortex-M0+ microcontroller 11.5 CoreMark data R R R R R NXP Semiconductors D D R A CPU performance/efficiency CPU/efficiency FT D 2 R A default 1.5 low-current 1 0.
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D D D D D A A A A A FT FT FT FT FT LPC82x D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R A FT FT A A R R D D The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG. and PDRUNCFG (for analog blocks) registers.
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D D D D D D R R D FT R R FT - 1990 2070 Combined analog and digital logic. ADC enabled in the PDRUNCFG register. - 11.7 Electrical pin characteristics aaa-013974 3.5 VOH OL (V) 3.2 -40 °C C 25 C °C 90 C °C 105 C °C 1.6 -40 °C C 25 °C C 90 °C C 105 °C C 2.9 1.5 2.6 1.4 2.3 1.3 1.2 2 0 4 8 12 16 20 IOH (mA) Conditions: VDD = 1.8 V; on pin PIO0_12. 24 0 20 40 60 IOH (mA) 80 Conditions: VDD = 3.3 V; on pin PIO0_12. Fig 25.
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D D D D D D R R FT FT FT FT D R R A FT FT FT A A R R D D D R F FT FT A A A R R D D D D FT FT A A R R D R -40 °C C 25 °C C 90 °C C 105 °C C A 45 D D FT D R -40 °C C 25 C °C 90 C °C 105 C °C 30 A A A A R R D D D aaa-013972 60 IOL (mA) FT FT FT FT FT aaa-013964 40 A A A A A LPC82x 32-bit ARM Cortex-M0+ microcontroller IOL (mA) R R R R R NXP Semiconductors A 20 30 10 15 0 0 0 0.1 0.2 0.3 0.4 0.5 VOL (V) 0.
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D D D D D D R R D A FT R D FT FT A A R R D R A FT D R A 2.3 2 4.5 IOH (mA) 6 Conditions: VDD = 1.8 V; standard port pins. 0 8 16 IOH (mA) 24 Conditions: VDD = 3.3 V; standard port pins. Fig 28. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH aaa-013979 0 Ipu (μA) (uA) aaa-013980 0 Ipu (μA) (uA) -14 -4 -28 -40 °C C 105 C °C 90 C °C 25 C °C -8 -42 105 °C C -40 °C C 90 °C C 25 °C C -12 -56 -16 -70 0 0.7 1.4 2.1 2.8 VI (V) 3.
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D D D D D D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R F FT FT A A A R R D D D aaa-013982 80 D FT FT A A R R D Ipd (μA) (uA) FT FT FT FT FT aaa-013981 35 A A A A A LPC82x 32-bit ARM Cortex-M0+ microcontroller Ipd pu (μA) (uA) R R R R R NXP Semiconductors D D 28 R A 60 FT D 14 -40 °C C 25 °C C 90 °C C 105 °C C 40 A -40 °C C 25 C °C 90 C °C 105 C °C R 21 20 7 0 0 0 0.7 1.4 2.1 2.8 VI (V) 3.
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D D D D D D R R D A FT R 1 - 25 MHz Tcy(clk) clock cycle time 40 - 1000 ns tCHCX clock HIGH time Tcy(clk)  0.4 - - ns tCLCX clock LOW time Tcy(clk)  0.4 - - ns tCLCH clock rise time - - 5 ns tCHCL clock fall time - - 5 ns F D oscillator frequency D Max fosc FT FT A A R R Unit D D R A FT D R A [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed.
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D D D D D D R R D A FT R D FT FT A A R R D R A FT D R A 110 Fig 32. Typical Internal RC oscillator frequency versus temperature Dynamic characteristics: Watchdog oscillator Symbol Parameter fosc(int) LPC82x Product data sheet Min Typ[1] Max Unit DIVSEL = 0x1F, FREQSEL = 0x1 in the WDTOSCCTRL register; [2][3] - 9.
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D D D D D FT FT FT FT FT D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D Table 15. Dynamic characteristics: I/O pins[1] Tamb = 40 C to +105 C; 3.0 V  VDD  3.6 V. A A A A A LPC82x 32-bit ARM Cortex-M0+ microcontroller 12.3.1 I/O pins R R R R R NXP Semiconductors Min Typ Max Unit pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.
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D D D D D D R R FT - s 0.5 - s Standard-mode 4.0 - s Fast-mode 0.6 - s Fast-mode Plus; on pins PIO0_10 and PIO0_11 0.26 - s Standard-mode 0 - s Fast-mode 0 - s Fast-mode Plus; on pins PIO0_10 and PIO0_11 0 - s Standard-mode 250 - ns Fast-mode 100 - ns Fast-mode Plus; on pins PIO0_10 and PIO0_11 50 - ns R FT FT A A R R A R A [2] Parameters are valid over operating temperature range unless otherwise specified.
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D D D D D D R R FT FT FT FT D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D A A A A R R D D D 6'$ FT FT FT FT FT W68 '$7 A A A A A LPC82x 32-bit ARM Cortex-M0+ microcontroller WI R R R R R NXP Semiconductors D D R W+' '$7 W9' '$7 A FT WI D W+,*+ R A 6&/ W/2: 6 I6&/ DDD Fig 33.
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D D D D D A A A A A FT FT FT FT FT LPC82x D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R A FT In master mode, the maximum supported bit rate is limited by the maximum system clock to 30 Mbit/s. In slave mode, assuming a set-up time of 3 ns for the external device and neglecting any PCB trace delays, the maximum supported bit rate is 1/(2 x (26 ns + 3 ns)) = 17 Mbit/s at 3.0 V <= VDD <= 3.
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D D D D D R R R R R FT FT D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D Tcy(clk) A A FT FT FT LPC82x A A A NXP Semiconductors D FT FT A A R R D SCK (CPOL = 0) D D R A SCK (CPOL = 1) FT D R A SSEL MOSI (CPHA = 0) tv(Q) tv(Q) DATA VALID (MSB) DATA VALID DATA VALID (MSB) MOSI (CPHA = 1) IDLE DATA VALID (MSB) DATA VALID (LSB) IDLE DATA VALID (MSB
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D D D D D R R R R R FT FT D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D Tcy(clk) A A FT FT FT LPC82x A A A NXP Semiconductors D FT FT A A R R D SCK (CPOL = 0) D D R A SCK (CPOL = 1) FT D R A SSEL MISO (CPHA = 0) tv(Q) tv(Q) DATA VALID (MSB) DATA VALID DATA VALID (MSB) MISO (CPHA = 1) IDLE DATA VALID (MSB) DATA VALID (LSB) IDLE DATA VALID (MSB
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D D D D D A A A A A FT FT FT FT FT LPC82x D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R A F FT The maximum USART bit rate is 10 Mbit/s in synchronous mode master mode and 10 Mbit/s in synchronous slave mode. FT A A R R D D D 12.3.6 USART interface R R R R R NXP Semiconductors D FT FT A A R R D D D Remark: USART functions can be assigned to all digital pins.
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D D D D D D R R D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D A FT Max Unit assertion - 2.25 - V de-assertion - 2.40 - V assertion - 2.54 - V de-assertion - 2.68 - V assertion - 2.85 - V de-assertion - 2.95 - V assertion - 1.46 - V de-assertion - 1.61 - V assertion - 2.05 - V de-assertion - 2.20 - V assertion - 2.34 - V de-assertion - 2.
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D D D D D D R R FT D R A - 30 MHz [3] - - 25 MHz 2.7 V <= VDD <= 3.6 V [2] - - 1.2 Msamples/s 2.4 V <= VDD < 2.7 V [3] - - 1 Msamples/s - +/- 2.5 - LSB differential linearity error Tamb = 105 °C EL(adj) integral non-linearity Tamb = 105 °C [6][4] - +/- 2.5 - LSB Tamb = 105 °C [7][4] - +/- 4.5 - LSB - +/- 0.5 - % 0.1 - - M full-scale error voltage 1.2 Msamples/s; Tamb = 105 °C input impedance fs = 1.
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D D D D D R R R R R A A FT FT FT FT FT LPC82x A A A D R R FT FT FT FT 32-bit ARM Cortex-M0+ microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D R R1 = 0.25 kΩ...2.5 kΩ FT D Cio R A ADCn_[1:11] DAC CDAC A ADCn_0 Rsw = 5 Ω...25 Ω Cio Cia aaa-011748 Fig 37.
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D D D D D R R R R R FT FT D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R A F FT gain error EG FT A A R R D D D D FT FT A A R R D offset error EO A A FT FT FT LPC82x A A A NXP Semiconductors D D 4095 R A FT D 4094 R A 4093 4092 4091 4090 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 4096 VIA (L
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D D D D D A A A A A FT FT FT FT FT LPC82x D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R F D - 940 mV - - s aaa-014424 0.910 VO ref (mV) (V) 0.905 0.900 0.895 0.890 -40 -10 20 50 80 temperature (°C) 110 VDD = 3.3 V; characterized through bench measurements on typical samples. Fig 39. Typical internal voltage reference output voltage Table 24.
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D D D D D D R R D D R R A FT R ns VIC = 1.5 V; 100 mV overdrive input - 130 - ns VIC = 1.5 V; rail-to-rail input [1][2] - 120 - ns VIC = 2.9 V; 100 mV overdrive input [1][2][4] - 220 - ns VIC = 2.9 V; rail-to-rail input [1][2] - 80 - ns VIC = 0.1 V; 100 mV overdrive input [1][2][4] - 240 - ns VIC = 0.1 V; rail-to-rail input [1][2] - 60 - ns VIC = 1.5 V; 100 mV overdrive input [1][2][4] - 160 - ns VIC = 1.
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D D D D D D R R FT % decimal code = 16 - +/- 1 - % decimal code = 24 - +/- 1 - % decimal code = 30 - +/- 1 - % decimal code = 31 - +/- 1 - % R A FT FT A D D R A © NXP Semiconductors N.V. 2014. All rights reserved. 66 of 81 FT Rev. 0.11 — 26 August 2014 R All information provided in this document is subject to legal disclaimers. D All peripherals except comparator, temperature sensor, and IRC turned off.
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D D D D D FT FT FT FT FT D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D 14.1 XTAL input A A A A A LPC82x 32-bit ARM Cortex-M0+ microcontroller 14. Application information R R R R R NXP Semiconductors D D The input voltage to the on-chip oscillators is limited to 1.8 V.
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D D D D D A A A A A FT FT FT FT FT LPC82x D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D /3& D D R / A ;7$/287 FT ;7$/,1 R R R R R NXP Semiconductors D R &3 A &/ ;7$/ 56 &; &; DDD Fig 41. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 27.
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D D D D D R R R R R A A FT FT FT FT FT LPC82x A A A D R R FT FT FT FT 32-bit ARM Cortex-M0+ microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout.
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D D D D D D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R F D FT Note 4 FT A A R R D ~10 kΩ - 100 kΩ A FT FT A A R R D D D SWD connector FT FT FT FT FT 3.3 V A A A A A LPC82x 32-bit ARM Cortex-M0+ microcontroller 3.3 V R R R R R NXP Semiconductors D D R 3 4 5 6 n.c. 7 8 n.c. FT 2 A SWDIO/PIO0_2 1 D SWCLK/PIO0_3 R A ~10 kΩ - 100 kΩ PIO0_8/XTALIN C1 n.c.
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D D D D D R R R R R A A FT FT FT FT FT LPC82x A A A D R R FT FT FT FT 32-bit ARM Cortex-M0+ microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D D R A F FT FT A A R R D D Unused pins with GPIO function should be configured as outputs set to LOW with their internal pull-up disabled.
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D D D D D A A A A A FT FT FT FT FT LPC82x D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 15. Package outline R R R R R NXP Semiconductors D FT A A R R D TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.
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D D D D D R R R R R A A FT FT FT FT FT LPC82x A A A D R R FT FT FT FT 32-bit ARM Cortex-M0+ microcontroller A A A A R R D D D NXP Semiconductors D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D HVQFN33: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.
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D D D D D A A A A A FT FT FT FT FT LPC82x D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D 16. Soldering R R R R R NXP Semiconductors D FT FT A A R R D Footprint information for reflow soldering of TSSOP20 package D D SOT360-1 R A FT D R A Hx Gx P2 (0.125) Hy Gy (0.
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D D D D D R R R R R FT FT D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D Footprint information for reflow soldering of HVQFN33 package A A FT FT FT LPC82x A A A NXP Semiconductors D FT FT A A R R D D D R A FT D R A Hx Gx see detail X P nSPx By Hy Gy SLy Ay nSPy C D SLx Bx Ax 0.60 solder land 0.
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D D D D D D R R FT D R A Universal Asynchronous Receiver/Transmitter 18. References LPC82x Product data sheet [1] User manual UM10800. [2] Errata sheet ES_LPC82XM. [3] I2C-bus specification UM10204. [4] Technical note ADC design guidelines: http://www.nxp.com/documents/technical_note/TN00009.pdf All information provided in this document is subject to legal disclaimers. Rev. 0.
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D D D D D D R R R A FT R A F FT FT A A R R D D D D FT Product data sheet - Modifications: • VREFP, VREFN usage specified. See Section 8.21 “Analog-to-Digital Converter (ADC)”. • Data sheet status changed to Product data sheet. Static char table split into three tables. LPC82X v.0.8 Modifications: • • Objective data sheet LPC82X v.0.8 - LPC82X v.0.7 TSSOP20 package removed. Comparator, internal voltage ref char data added. LPC82X v.0.
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D D D D D A A A A A FT FT FT FT FT LPC82x D R R FT FT FT FT A A A A R R D D D 32-bit ARM Cortex-M0+ microcontroller D R R A FT FT FT A A R R D D D R F D FT FT A A R R D 20.1 Data sheet status A FT FT A A R R D D D 20. Legal information R R R R R NXP Semiconductors D D R Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development.
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D D D D D D R R D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D D D R A FT 20.4 Trademarks D For sales office addresses, please send an email to: salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 0.11 — 26 August 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 79 of 81 A I2C-bus — logo is a trademark of NXP B.V.
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D D D D D D R R D A FT R A FT FT A 22 23 23 24 24 25 25 R R D D R A A 80 of 81 R © NXP Semiconductors N.V. 2014. All rights reserved. D 25 25 25 26 26 26 26 26 27 27 27 28 28 28 29 29 29 30 31 32 33 33 34 36 39 45 46 47 50 50 50 51 53 53 53 53 56 59 60 FT Rev. 0.11 — 26 August 2014 F D D All information provided in this document is subject to legal disclaimers. A FT FT A A R R D D D Product data sheet R R FT FT A A R R D D D Features. . . . . . . . . . . .
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D D D D D D R R FT FT FT FT A A A A R R D D D D R R A FT FT FT A A R R D D D R A F FT FT A A R R D D D D FT FT A A R R D D D R A FT D R A 14.4 14.5 15 16 17 18 19 20 20.1 20.2 20.3 20.4 21 22 FT FT FT FT FT 14.3 BOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Comparator and internal voltage reference . . 64 Application information. . . . . . . . . . . . . .