Datasheet

DRAFT DRAFT DRAFT DR DRAFT DRAFT DRAFT
D
RAF
DRAFT DRAFT DRA
F
T D
RAFT DR
AFT D
DRA
F
T DRAFT DRAFT
D
RAFT
DRAFT
D
RAFT
DRA
LPC82x All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 0.11 — 26 August 2014 57 of 81
NXP Semiconductors
LPC82x
32-bit ARM Cortex-M0+ microcontroller
T
cy(clk)
= CCLK/DIVVAL with CCLK = system clock frequency. DIVVAL is the SPI clock divider. See the LPC82x User manual.
Fig 34. SPI master timing
SCK (CPOL = 0)
MOSI (CPHA = 1)
SSEL
MISO (CPHA = 1)
T
cy(clk)
t
DS
t
DH
t
v(Q)
DATA VALID (LSB) DATA VALID
t
v(Q)
SCK (CPOL = 1)
DATA VALID (LSB)
DATA VALID
MOSI (CPHA = 0)
MISO (CPHA = 0)
t
DS
t
DH
DATA VALID (MSB) DATA VALID (MSB)DATA VALID
DATA VALID (LSB)
DATA VALID (LSB)
t
v(Q)
DATA VALID (MSB)
DATA VALID
t
v(Q)
aaa-013462-m1
DATA VALID (MSB)
DATA VALID (MSB)
DATA VALID (MSB)
DATA VALID (MSB)
IDLE
IDLE
IDLE
IDLE
DATA VALID (MSB)