Datasheet

FUNCTIONAL DEVICE OPERATION
PROGRAMMABILITY
Analog Integrated Circuit Device Data
40 Freescale Semiconductor
MC13892
FUNCTIONAL DEVICE OPERATION
PROGRAMMABILITY
INTERFACING OVERVIEW AND CONFIGURATION OPTIONS
The MC13892 contains a number of programmable registers for control and communication. The majority of registers are
accessed through a SPI interface in a typical application. The same register set may alternatively be accessed with an I
2
C
interface that is muxed on SPI pins. The following table describes the muxed pin options for the SPI and I
2
C interfaces. Further
details for each interface mode follow in this chapter.
SPI INTERFACE
The MC13892 contains a SPI interface port, which allows access by a processor to the register set. Via these registers, the
resources of the IC can be controlled. The registers also provide status information about how the IC is operating, as well as
information on external signals.
The SPI interface pins can be reconfigured for reuse as an I
2
C interface. As a result, a configuration protocol mandates that
the CS pin is held low during a turn on event for the IC (a weak pull-down is integrated on the CS pin. With the CS pin held low
during startup (as would be the case if connected to the CS driver of an unpowered processor, due to the integrated pull-down),
the bus configuration will be latched for SPI mode.
The SPI port utilizes 32-bit serial data words comprised of 1 write/read_b bit, 6 address bits, 1 null bit, and 24 data bits. The
addressable register map spans 64 registers of 24 data bits each.
The general structure of the register set is given in the following table. Bit names, positions, and basic descriptions are
provided in SPI Bitmap. Expanded bit descriptions are included in the following functional chapters for application guidance. For
brevity's sake, references are occasionally made herein to the register set as the “SPI map” or “SPI bits”, but note that bit access
is also possible through the I
2
C interface option, so such references are implied as generically applicable to the register set
accessible by either interface.
Table 7. SPI / I
2
C Bus Configuration
Pin Name SPI Mode Functionality I2C Mode Functionality
CS Configuration
(43)
, Chip Select Configuration
(44)
CLK SPI Clock SCL: I
2
C bus clock
MISO Master In, Slave Out (data output) SDA: Bi-directional serial data line
MOSI Master Out, Slave In (data input) A0 Address Selection
(45)
Notes
43. CS held low at Cold Start configures interface for SPI mode; once activated, CS functions as the SPI Chip Select.
44. CS tied to VCORE at Cold Start configures interface for I
2
C mode; the pin is not used in I
2
C mode other than for configuration.
45. In I
2
C mode, the MOSI pin hard wired to ground or VCORE is used to select between two possible addresses.
Table 8. Register Set
Register Register Register Register
0 Interrupt Status 0 16 Unused 32 Regulator Mode 0 48 Charger 0
1 Interrupt Mask 0 17 Unused 33 Regulator Mode 1 49 USB0
2 Interrupt Sense 0 18 Memory A 34 Power Miscellaneous 50 Charger USB1
3 Interrupt Status 1 19 Memory B 35 Unused 51 LED Control 0
4 Interrupt Mask 1 20 RTC Time 36 Unused 52 LED Control 1
5 Interrupt Sense 1 21 RTC Alarm 37 Unused 53 LED Control 2
6 Power Up Mode Sense 22 RTC Day 38 Unused 54 LED Control 3
7 Identification 23 RTC Day Alarm 39 Unused 55 Unused
8 Unused 24 Switchers 0 40 Unused 56 Unused
9 ACC 0 25 Switchers 1 41 Unused 57 Trim 0
10 ACC 1 26 Switchers 2 42 Unused 58 Trim 1
11 Unused 27 Switchers 3 43 ADC 0 59 Te s t 0