Datasheet

FUNCTIONAL DEVICE OPERATION
PROGRAMMABILITY
Analog Integrated Circuit Device Data
Freescale Semiconductor 43
MC13892
Table 10. SPI Interface Timing Specifications
Parameter Description t min (ns)
t
SELSU
Time CS has to be high before the first rising edge of CLK
15
t
SELHLD
Time CS has to remain high after the last falling edge of CLK
15
t
SELLOW
Time CS has to remain low between two transfers
15
t
CLKPER
Clock period of CLK
38
t
CLKHIGH
Part of the clock period where CLK has to remain high
15
t
CLKLOW
Part of the clock period where CLK has to remain low
15
t
WRTSU
Time MOSI has to be stable before the next rising edge of CLK
4.0
t
WRTHLD
Time MOSI has to remain stable after the rising edge of CLK
4.0
t
RDSU
Time MISO will be stable before the next rising edge of CLK
4.0
t
RDHLD
Time MISO will remain stable after the falling edge of CLK
4.0
t
RDEN
Time MISO needs to become active after the rising edge of CS
4.0
t
RDDIS
Time MISO needs to become inactive after the falling edge of CS
4.0
Notes
46. This table reflects a maximum SPI clock frequency of 26 MHz
Table 11. SPI Interface Logic IO Specifications
Parameter Condition Min Typ Max Units
Input Low CS, MOSI, CLK
0.0 – 0.3*SPIVCC V
Input High CS, MOSI, CLK
0.7*SPIVCC – SPIVCC+0.3 V
Output Low MISO, INT Output sink 100 μA
0 – 0.2 V
Output High MISO, INT Output source 100 μA
SPIVCC-0.2 – SPIVCC V
SPIVCC Operating Range
1.75 – 3.1 V
MISO Rise and Fall Time
CL = 50 pF, SPIVCC = 1.8 V
SPIDRV[1:0] = 00 (default)
– 11 – ns
SPIDRV[1:0] = 01
– 6.0 – ns
SPIDRV[1:0] = 10
– High Z – ns
SPIDRV[1:0] = 11
– 22 – ns