Datasheet

FUNCTIONAL DEVICE OPERATION
I2C INTERFACE
Analog Integrated Circuit Device Data
Freescale Semiconductor 47
MC13892
Additional sense bits are available to reflect the state of the power up mode selection pins, as summarized in Table 13.
LOBATHI LOBATHM LOBATHS
Low battery warning
Sense is 1 if above LOBATH
threshold.
Dual 30 μs page 54
VBUSVALIDI VBUSVALIDM VBUSVALIDS Detects A-Session Valid on VBUS Dual
L2H: 20-
24
ms
H2L: 8-
12
ms
page 111
IDFLOATI IDFLOATM IDFLOATS
ID floating detect. Sense is 1 if
above threshold
Dual 90 μs page 111
IDGNDI IDGNDM IDGNDS
USB ID ground detect. Sense is 1
if not to ground
Dual 90 μs page 111
IDFACTORYI IDFACTORYM IDFACTORYS
ID voltage for Factory mode detect
Sense is 1 if above threshold
Dual 90 μs page 111
CHRGSE1BI CHRGSE1BM CHRSE1BS
Wall charger detect
Regulator short-circuit protection
tripped
Dual
L2H
1.0 ms
200 μs
page 89
SCPI SCPS –
Short circuit protection trip
detection
L2H 0 page 71
BATTDETBI BATTDETBM BATTDETBS Battery removal detect Dual 30 ms page 100
1HZI 1HZM – 1.0 Hz time tick L2H 0 page 49
TODAI TODAM – Time of day alarm L2H 0 page 49
PWRON1I PWRON1M PWRON1S
PWRON1 event
Sense is 1 if pin is high.
H2L 30 ms
(1)
page 54
L2H 30 ms page 54
PWRON2I PWRON2M PWRON2S
PWRON2 event
Sense is 1 if pin is high.
H2L 30 ms
(47)
page 54
L2H 30 ms page 54
PWRON3I PWRON3M PWRON3S
PWRON3 event
Sense is 1 if pin is high.
H2L 30 ms
(47)
page 54
L2H 30 ms page 54
SYSRSTI SYSRSTM –
System reset through PWRONx
pins
L2H 0 page 54
WDIRESETI WDIRESETM – WDI silent system restart L2H 0 page 54
PCI PCM – Power cut event L2H 0 page 54
WARMI WARMM – Warm Start event L2H 0 page 54
MEMHLDI MEMHLDM – Memory Hold event L2H 0 page 54
CLKI CLKM CLKS
Clock source change
Sense is 1 if source is XTAL
Dual 0 page 49
RTCRSTI RTCRSTM –
RTC reset or intrusion has
occurred
L2H 0 page 49
THWARNHI THWARNHM THWARNHS
Thermal warning higher threshold
Sense is 1 if above threshold
Dual 30 ms page 71
THWARNLI THWARNLM THWARNLS
Thermal warning lower threshold
Sense is 1 if above threshold
Dual 30 ms page 71
LPBI LPBM LPBS Low-power boot interrupt Dual 1.0 ms page 89
Notes
47. Debounce timing for the falling edge can be extended with PWRONxDBNC[1:0]; refer to Power Control System for details.
Table 12. Interrupt, Mask and Sense Bits
Interrupt Mask Sense Purpose Trigger
DebounceTi
me
Section