Datasheet

FUNCTIONAL DEVICE OPERATION
CLOCK GENERATION AND REAL TIME CLOCK
Analog Integrated Circuit Device Data
50 Freescale Semiconductor
MC13892
OSCILLATOR APPLICATION GUIDELINES
The guidelines below may prove to be helpful in providing a crystal oscillator that starts reliably and runs with minimal jitter.
PCB leakage: The RTC amplifier is a low-current circuit. Therefore, PCB leakage may significantly change the operating point
of the amplifier and even the drive level to the crystal. (Changing the drive level to the crystal may change the aging rate, jitter,
and even the frequency at a given load capacitance.) The traces should be kept as short as possible to minimize the leakage,
and good PCB manufacturing processes should be maintained.
Layout: The traces from the MC13892 to the crystal, load capacitance, and the RTC Ground are sensitive. They must be kept
as short as possible with minimal coupling to other signals. The signal ground for the RTC is to be connected to GNDRTC, and
via a single connection, GNDRTC to the system ground. The CLK32K and CLK32KMCU square wave outputs must be kept away
from the crystal / load capacitor leads, as the sharp edges can couple into the circuit and lead to excessive jitter. The crystal /
load capacitance leads and the RTC Ground must form a minimal loop area.
Crystal Choice: Generally speaking, crystals are not interchangeable between manufacturers, or even different packages for
a given manufacturer. If a different crystal is considered, it must be fully characterized with the MC13892 before it can be
considered.
Tuning Capacitors: The nominal load capacitance is 9.0 pF, therefore the total capacitance at each node should be 18 pF,
composed out of the load capacitance, the effective input capacitance at each pin, plus the PCB stray capacitance for each pin.
SRTC SUPPORT
The MC13892 provides support for processors which have an integrated SRTC for Digital Rights Management (DRM), by
providing a VSRTC voltage to bias the SRTC module of the processor, as well as a CLK32KMCU at the VSRTC output level.
When configured for DRM mode (SPI bit DRM = 1), the CLK32MCU driver will be kept enabled through all operational states,
to ensure that the SRTC module always has its reference clock. If DRM
= 0, the CLK32KMCU driver will not be maintained in the
Off state. Refer to
Table 23 for the operating behavior of the CLK32KMCU output in User Off, Memory Hold, User off Wait, and
internal MEMHOLD PCUT modes.
It is also necessary to provide a means for the processor to do an RTC initiated wake-up of the system, if it has been
programmed for such capability. This can be accomplished by connecting an open drain NMOS driver to the PWRON pin of the
MC13892, so that it is in effect a parallel path for the power key. The MC13892 will not be able to discern the turn on event from
a normal power key initiated turn on, but the processor should have the knowledge, since the RTC initiated turn on is generated
locally.
Table 16. Crystal Oscillator Main Characteristics
Parameter Condition Min Typ Max Units
Operating Voltage Oscillator and RTC Block from BP 1.2 – 4.65 V
Coin cell Disconnect Threshold At LICELL 1.8 – 2.0 V
RTC oscillator startup time Upon application of power - – 1.0 sec
XTAL1 Input Level External clock source 0.3 – - V
PP
XTAL1 Input Range External clock source -0.5 – 1.2 V
Output Low CLK32K,
CLK32KMCU
Output sink 100 μA 0 – 0.2 V
Output High
CLK32K Output source 100 μA SPIVCC-0.2 – SPIVCC V
CLK32KMCU Output source 100 μA VSRTC-0.2 – VSRTC V
CLK32K Rise and Fall Time
CL=50 pF
CLK32KDRV[1:0] = 00 (default) – 22 – ns
CLK32KDRV[1:0] = 01 – 11 – ns
CLK32KDRV[1:0] = 10 – High Z – ns
CLK32KDRV[1:0] = 11 – 44 – ns
CLD32KMCU Rise and Fall Time CL=12 pF – 22 – ns
CLK32K and CLK32KMCU
Output Duty Cycle
Crystal on XTAL1, XTAL2 pins 45 – 55 %