Datasheet

Analog Integrated Circuit Device Data
105 Freescale Semiconductor
MC34708
Functional Block Description
7.9 Serial Interfaces
The IC contains a number of programmable registers for control and communication. The majority of registers are accessed
through a SPI interface in a typical application. The same register set may alternatively be accessed with an I
2
C interface muxed
on SPI pins.
Table 98 describes the muxed pin options for the SPI and I
2
C interfaces; further details for each interface mode
follow.
7.9.1 SPI Interface
The IC contains a SPI interface port which allows access by a processor to the register set. Via these registers, the resources of
the IC can be controlled. The registers also provide status information about how the IC is operating, as well as information on
external signals.
Because the SPI interface pins can be reconfigured for reuse as an I
2
C interface, a configuration protocol mandates the CS pin
is held low during a turn on event for the IC (a weak pull-down is integrated on the CS pin). The state of CS is latched in during
the initialization phase of a Cold Start sequence, ensuring the I
2
C bus is configured before the interface is activated. With the CS
pin held low during startup (as would be the case if connected to the CS driver of an unpowered processor due to the integrated
pull down), the bus configuration will be latched for SPI mode.
The SPI port utilizes 32-bit serial data words comprised of 1 write/read_b bit, 6 address bits, 1 null bit, and 24 data bits. The
addressable register map spans 64 registers of 24 data bits each. The map is not fully populated, but it follows the legacy
conventions for bit positions corresponding to common functionality with previous generation FSL products.
7.9.1.1 SPI Interface Description
For a SPI read, the first bit sent to the IC must be a zero indicating a SPI read cycle. Next, the six bit address is sent MSB first.
This is followed by one dead bit to allow for more address decode time. The MC34708 will clock the above bits in on the rising
edge of the SPI clock. The 24 data bits are then driven out on the MISO pin on the falling edge of the SPI clock, so the master
can clock them in on the rising edge of the SPI clock.
ID Detection (Continued)
t
VCBL
Video Cable Detection Time (Video Cable Detection Current Source On
Time)
- 20 -
ms
t
RMTCON_DG
Key Press Comparator Debounce Time
- 20 -
ms
Table 98. SPI / I
2
C Bus Configuration
Pin Name SPI Mode Functionality I
2
C Mode Functionality
CS Configuration
(71)
, Chip Select Configuration
(72)
CLK SPI Clock SCL: I
2
C bus clock
MISO Master In, Slave Out (data output) SDA: Bi-directional serial data line
MOSI Master Out, Slave In (data input) A0 Address Selection
(73)
Notes
71. CS held low at Cold Start, configures the interface for SPI mode; once activated, CS functions as the SPI Chip Select.
72. CS tied to VCOREDIG at Cold Start, configures the interface for I
2
C mode; the pin is not used in I
2
C mode, other than for configuration.
73. In I
2
C mode, the MOSI pin is hardwired to ground, or VCOREDIG is used to select between two possible addresses.
Table 97. USB Interface Electrical Characteristics
Characteristics noted under conditions BP = 3.6 V, V
BUS
= 5.0 V, - 40 C  T
A
 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and T
A
= 25 °C under nominal conditions, unless otherwise noted.
Symbol Characteristic Min Typ Max Unit Notes