Datasheet

Analog Integrated Circuit Device Data
107 Freescale Semiconductor
MC34708
Functional Block Description
7.9.1.2 SPI Timing Requirements
The following diagram and table summarize the SPI timing requirements. The SPI input and output levels are set via the SPIVCC
pin, by connecting it to the desired supply. This would typically be tied to SW5 and programmed for 1.80 V. The strength of the
MISO driver is programmable through the SPIDRV [1:0] bits. See Thermal Protection Thresholds for detailed SPI electrical
characteristics.
Figure 35. SPI Interface Timing Diagram
Table 99. SPI Interface Timing Specifications
(74)
Parameter Description T min (ns)
t
SELSU
Time CS has to be high before the first rising edge of CLK
15
t
SELHLD
Time CS has to remain high after the last falling edge of CLK
15
t
SELLOW
Time CS has to remain low between two transfers
15
t
CLKPER
Clock period of CLK
38
t
CLKHIGH
Part of the clock period where CLK has to remain high
15
t
CLKLOW
Part of the clock period where CLK has to remain low
15
t
WRTSU
Time MOSI has to be stable before the next rising edge of CLK
4.0
t
WRTHLD
Time MOSI has to remain stable after the rising edge of CLK
4.0
t
RDSU
Time MISO will be stable before the next rising edge of CLK
4.0
t
RDHLD
Time MISO will remain stable after the falling edge of CLK
4.0
t
RDEN
Time MISO needs to become active after the rising edge of CS
4.0
t
RDDIS
Time MISO needs to become inactive after the falling edge of CS
4.0
Notes
74. This table reflects a maximum SPI clock frequency of 26 MHz.
CS
CLK
MOSI
MISO
t
CLKPER
t
CLKLOW
t
DKHIGH
t
SELSU
t
SELHLD
t
SELLOW
t
RDDIS
t
RDHLD
t
RDSU
t
RDEN
t
WRTSU
t
WRTHLD