Datasheet
Analog Integrated Circuit Device Data
Freescale Semiconductor 128
MC34708
Functional Block Description
Table 132. Register 27, Regulator 5 Voltage
Name Bit # R/W Reset Default Description
SW5[4:0] 4-0 R/WM NONE *
SW4 setting in normal mode
Unused 9-5 R *
Not available
SW5STBY[4:0] 14-10 R/WM NONE *
SW5 setting in Standby mode
Unused 23-15 R 0x000
Not available
Table 133. Register 28, Regulators 1 & 2 Operating Mode
Name Bit # R/W Reset Default Description
SW1AMODE[3:0] 3-0 R/W RESETB 0xA
SW1A operating mode
SW1AMHMODE 4 R/W OFFB 0x0
SW1A Memory Hold mode
SW1AUOMODE 5 R/W OFFB 0x0
SW1A User Off mode
SW1DVSSPEED[1:0] 7-6 R/W RESETB 0x1
SW1 DVS1 speed
Unused 13-8 R 0x00
Not available
SW2MODE[3:0]
(81)
17-14 R/W RESETB 0xA
SW2 operating mode
SW2MHMODE 18 R/W OFFB 0x0
SW2 Memory Hold mode
SW2UOMODE 19 R/W OFFB 0x0
SW2 User Off mode
SW2DVSSPEED[1:0] 21-20 R/W RESETB 0x01
SW2 DVS1 speed
PLLEN 22 R/W RESETB 0x1
PLL enable
PLLX 23 R/W RESETB 0x0
PLL multiplication factor
Notes
81. SWxMODE[3:0] bits will be reset to their default values by the startup sequencer, based on PUMS settings. An enabled
switch will default to APS mode for both Normal and Standby operation.
Table 134. Register 29, Regulators 3, 4, and 5 Operating Mode
Name Bit # R/W Reset Default Description
SW3MODE[3:0] 3-0 R/W RESETB 0xA
SW3 operating mode
SW3MHMODE 4 R/W OFFB 0x0
SW3 Memory Hold mode
SW3UOMODE 5 R/W OFFB 0x0
SW3 User Off mode
SW4AMODE[3:0] 9-6 R/W RESETB 0xA
SW4A operating mode
SW4AMHMODE 10 R/W OFFB 0x0
SW4A Memory Hold mode
SW4AUOMODE 11 R/W OFFB 0x0
SW4A User Off mode
SW4BMODE[3:0] 15-12 R/W RESETB 0xA
SW4B operating mode
SW4BMHMODE 16 R/W OFFB 0x0
SW4B Memory Hold mode
SW4BUOMODE 17 R/W OFFB 0x0
SW4B User Off mode
SW5MODE[3:0]
(82)
21-18 R/W RESETB 0xA
SW5 operating mode
SW5MHMODE 22 R/W OFFB 0x0
SW5 Memory Hold mode
SW5UOMODE 23 R/W OFFB 0x0
SW5 User Off mode
Notes
82. SWxMODE[3:0] bits will be reset to their default values by the startup sequencer, based on PUMS settings. An enabled
regulator will default to APS mode for both Normal and Standby operation.