Datasheet

Analog Integrated Circuit Device Data
129 Freescale Semiconductor
MC34708
Functional Block Description
Table 135. Register 30, Regulator Setting 0
Name Bit # R/W Reset Default Description
VGEN1[2:0] 2-0 R/WM RESETB *
VGEN1 setting
Unused 3 R 0x0
Not available
VDAC[1:0] 5-4 R/WM RESETB *
VDAC setting
VGEN2[2:0] 8-6 R/WM RESETB *
VGEN2 setting
VPLL[1:0] 10-9 R/WM RESETB *
VPLL setting
VUSB2[1:0] 12-11 R/WM RESETB *
VUSB2 setting
Unused 23-13 R 0x000
Not available
Table 136. Register 31, SWBST Control
Name Bit # R/W Reset Default Description
SWBST[1:0] 1-0 R/W NONE *
SWBST setting
SWBSTMODE[1:0] 3-2 R/W RESETB 0x2
SWBST mode
Spare 4 R/W RESETB 0x0
Not available
SWBSTSTBYMODE[1:0] 6-5 R/W RESETB 0x2
SWBST standby mode
Spare 7 R/W RESETB 0x0
Not available
Unused 23-8 R 0x0000
Not available
Table 137. Register 32, Regulator Mode 0
Name Bit # R/W Reset Default Description
VGEN1EN 0 R/W NONE *
VGEN1 enable
VGEN1STBY 1 R/W RESETB 0x0
VGEN1 controlled by standby
VUSBSEL 2 R/W NONE *
Slave or Host configuration for VBUS
VUSBEN 3 R/W RESETB 0x1
VUSB enable (PUMS4:1=[0100]). Also reset to 1 by invalid
VBUS
VDACEN 4 R/W NONE *
VDAC enable
VDACSTBY 5 R/W RESETB 0x0
VDAC controlled by standby
VDACMODE 6 R/W RESETB 0x0
VDAC operating mode
Unused 9-7 R 0x0
Not available
VREFDDREN 10 R/W NONE *
VREFDDR enable
VGEN2CONFIG 11 R/W NONE *
PUMS5 Tied to ground = 0: VGEN2 with external PNP
PUMS5 Tied to VCROREDIG =1:VGEN2 internal PMOS
VGEN2EN 12 R/W NONE *
VGEN2 enable
VGEN2STBY 13 R/W RESETB 0x0
VGEN2 controlled by standby
VGEN2MODE 14 R/W RESETB 0x0
VGEN2 operating mode
VPLLEN 15 R/W NONE *
VPLL enable
VPLLSTBY 16 R/W RESETB 0x0
VPLL controlled by standby
VUSB2CONFIG 17 R/W NONE *
PUMS5 Tied to ground = 0: VUSB2 with external PNP
PUMS5 Tied to VCROREDIG =1:VUSB2 internal PMOS
VUSB2EN 18 R/W NONE *
VUSB2 enable