Datasheet

Analog Integrated Circuit Device Data
Freescale Semiconductor 24
MC34708
Functional Block Description
7 Functional Block Description
7.1 Startup Requirements
When power is applied, there is an initial delay of 8.0 ms during which the core circuitry is enabled. The switching and linear
regulators are then sequentially enabled in time slot steps of 2.0
ms. This allows the PMIC to limit the inrush current.
The outputs of the switching regulators not enabled are discharged with weak pull-downs on the output to ensure a proper power-
up sequence. Any undervoltage detection at BP is masked while the power-up sequencer is running. When the switching
regulators are enabled, they will start in PWM mode. After 3.0
ms, the switching regulators will transition to the mode
programmed in the SPI register map.
The Power-up mode select pins PUMSx (x = 1, 2, 3, 4, and 5) are used to configure the start-up characteristics of the regulators.
Supply enabling and output level options are selected by hardwiring the PUMSx pins. It is recommended to minimize the load
during system boot-up by supplying only the essential voltage domains. This allows the start-up transients to be minimized after
which the rest of the system power tree can be brought up by software. The PUMSx pins also allow optimization of the supply
sequence and default values. Software code can load the required programmable options without any change to hardware.
The state of the PUMSx pins are latched before any of the regulators are enabled, with the exception of VCORE. PUMSx options
and start-up configurations are robust to a PCUT event, whether occurring during normal operation or during the 8.0 ms of pre-
sequencer initialization, i.e. the system will not end up in an unexpected / undesirable consumption state.
Table 11 shows the initial setup for the voltage level of the switching and linear regulators, and whether they get enabled.
Table 11. Power Up Defaults
i.MX Reserved
53
LPM
53
DDR2
53
DDR3
53
LVDDR3
53
LVDDR2
50
MDDR
50
LPDDR2
50
LPDDR2
50
MDDR
50
LPDDR2
50
MDDR
PUMS[4:1] 0000-0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
PUMS5=0
VUSB2
VGEN2
Reserved
Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP Ext PNP
PUMS5=1
VUSB2
VGEN2
Reserved
Internal
PMOS
Internal
PMOS
Internal
PMOS
Internal
PMOS
Internal
PMOS
Internal
PMOS
Internal
PMOS
Internal
PMOS
Internal
PMOS
Internal
PMOS
Internal
PMOS
SW1A
(VDDGP)
Reserved 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1
SW1B
(VDDGP)
Reserved 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1 1.1
SW2
(31)
(VCC)
Reserved 1.225 1.3 1.3 1.3 1.3 1.2 1.2 1.2 1.2 1.2 1.2
SW3
(31)
(VDDA)
Reserved 1.2 1.3 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2
SW4A
(31)
(DDR/SYS)
Reserved 1.5 1.8 1.5 1.35 1.2 1.8 1.2 3.15 3.15 3.15 3.15
SW4B
(31)
(DDR/SYS)
Reserved 1.5 1.8 1.5 1.35 1.2 1.8 1.2 1.2 1.8 1.2 1.8
SW5
(31)
(I/O)
Reserved 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8
SWBST Reserved Off Off Off Off Off Off Off Off Off Off Off
VUSB
(32)
Reserved 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3
VUSB2 Reserved 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5