Datasheet

Analog Integrated Circuit Device Data
25 Freescale Semiconductor
MC34708
Functional Block Description
The power up sequence is shown in Tables 12 and 13. VCOREDIG, VSRTC, and VCORE, are brought up in the pre-sequencer
startup.
VSRTC Reserved 1.2 1.3 1.3 1.3 1.3 1.2 1.2 1.2 1.2 1.2 1.2
VPLL Reserved 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8
VREFDDR Reserved On On On On On On On On On On On
VDAC Reserved 2.775 2.775 2.775 2.775 2.775 2.5 2.5 2.5 2.5 2.5 2.5
VGEN1 Reserved 1.2 1.3 1.3 1.3 1.3 1.2 1.2 1.2 1.2 1.2 1.2
VGEN2 Reserved 2.5 2.5 2.5 2.5 2.5 3.1 3.1 3.1 3.1 2.5 2.5
Notes
31. The SWx node are activated in APS mode when enabled by the startup sequencer.
32. VUSB regulator is only enabled if 5.0 V is present on VBUS. By default VUSB will be supplied by VBUS. SWBST = 5.0 V powers up as
does VUSB, regardless of 5.0
V present on UVBUS. By default VUSB is supplied by SWBST.
Table 12. Power Up Sequence i.MX53
Tap x 2.0 ms PUMS [4:1] = [0101,0110,0111,1000,1001] (i.MX53)
0 SW2 (VCC)
1 VPLL (NVCC_CKIH = 1.8 V)
2 VGEN2 (VDD_REG= 2.5 V, external PNP
3 SW3 (VDDA)
4 SW1A/B (VDDGP)
5 SW4A/B, VREFDDR (DDR/SYS)
6
7 SW5 (I/O), VGEN1
8 VUSB
(33)
, VUSB2
9 VDAC
Notes:
33. The VUSB regulator is only enabled if 5.0 V is present on the VBUS pin. By
default VUSB will be supplied by the VBUS pin.
Table 11. Power Up Defaults
i.MX Reserved
53
LPM
53
DDR2
53
DDR3
53
LVDDR3
53
LVDDR2
50
MDDR
50
LPDDR2
50
LPDDR2
50
MDDR
50
LPDDR2
50
MDDR