Datasheet

Analog Integrated Circuit Device Data
Freescale Semiconductor 26
MC34708
Functional Block Description
7.2 Bias and References Block Description and Application
Information
All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at VCOREREF. The
bandgap and the rest of the core circuitry is supplied from VCORE. The performance of the regulators is directly dependent on
the performance of VCORE and the bandgap. No external DC loading is allowed on VCORE, VCOREDIG, and REFCORE.
VCOREDIG is kept powered as long as there is a valid supply and/or coin cell.
Table 14 shows the main characteristics of the
core circuitry.
Table 13. Power Up Sequence i.MX50
Tap x 2.0 ms PUMS [4:1] = [0100, 1011, 1100, 1101, 1110, 1111] (i.MX50/I.MX53)
0 SW2
1 SW3
2 SW1A/B
3 VDAC
4 SW4A/B, VREFDDR
5 SW5
6 VGEN2, VUSB2
7 VPLL
8 VGEN1
9 VUSB
(34)
Notes:
34. The VUSB regulator is only enabled if 5.0 V is present on the VBUS pin. By
default VUSB will be supplied by the VBUS pin.
Table 14. Core Voltages Electrical Specifications
Characteristics noted under conditions BP = 3.6 V, V
BUS
= 5.0 V, - 40 C  T
A
 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and T
A
= 25 °C under nominal conditions, unless otherwise noted.
Symbol Characteristic Min Typ Max Unit Notes
VCOREDIG (DIGITAL CORE SUPPLY)
V
COREDIG
Output voltage
• ON mode
• OFF mode with good battery and RTC mode
-
-
1.5
1.2
-
-
V
(35)
C
COREDIG
V
COREDIG
bypass capacitor
- 1.0 - F
VDDLP (DIGITAL CORE SUPPLY - LOWER POWER)
V
DDLP
Output voltage
• ON mode with good battery
• OFF mode with good battery
• RTC mode
-
-
-
1.5
1.2
1.2
-
-
-
V
(36)
C
DDLP
V
DDLP
bypass capacitor
- 100 - pF
(37)