Datasheet
Analog Integrated Circuit Device Data
29 Freescale Semiconductor
MC34708
Functional Block Description
7.3.2 SRTC Support
When configured for DRM mode (SPI bit DRM = 1), the CLK32KMCU driver will be kept enabled through all operational states
to ensure the SRTC module always has its reference clock. If DRM
= 0, the CLK32KMCU driver will not be maintained in the Off
state.
It is also necessary to provide a means for the processor to do an RTC initiated wake-up of the system if it has been programmed
for such capability. This can be accomplished by connecting an open drain NMOS driver to the PWRON pin of the MC34708
PMIC, so it is in effect, a parallel path for the power key. The MC34708 PMIC will not be able to discern the turn on event from
a normal power key initiated turn on, but the processor should have the knowledge, since the RTC initiated turn on is generated
locally.
Figure 5. SRTC Block Diagram
7.3.2.1 VSRTC
The VSRTC regulator provides the CLK32KMCU output level. Additionally, it is used to bias the Low Power SRTC domain of the
SRTC module integrated on certain FSL processors. The VSRTC regulator is enabled as soon as the RTCPORB is detected.
The VSRTC regulator cannot be disabled.
Depending on the configuration of the PUMS[4:0] pins, the VSRTC voltage will be set to 1.3 or 1.2 V. With PUMS[4:0] = (0110,
0111, 1000, or 1001) VSRTC will be set to 1.3
V in ON mode (ON, ON Standby and ON Standby Low Power modes). In OFF
and Coin Cell modes the VSRTC voltage will drop to 1.2 V with the PUMS[4:0] = (0110, 0111, 1000, or 1001). With PUMS[4:0]
≠ (0110, 0111, 1000, or 1001), VSRTC will be set to 1.2
V for all modes (ON, ON Standby, LPM ON Standby, OFF, and Coin Cell).
Table 16. VSRTC Electrical Specifications
Characteristics noted under conditions BP = 3.6 V, V
BUS
= 5.0 V, - 40 C T
A
85 C, unless otherwise noted. Typical values
at BP = 3.6
V and T
A
= 25 °C under nominal conditions, unless otherwise noted.
Symbol Characteristic Min Typ Max Unit Notes
GENERAL
V
SRTCIN
Operating Input Voltage Range V
INMIN
to V
INMAX
• Valid Coin Cell range
•Valid BP
1.8
1.8
-
-
3.6
4.5
V
I
SRTC
Operating Current Load Range IL
MIN
to IL
MAX
0.0 - 50 A
CO
SRTC
Bypass Capacitor Value
- 0.1 - F
+
+
-
-
34708
VCOREDIG
PWRONx
SPIVCC=1.8 V
GP Domain=1.1 V
LP Dominant=1.2 V
VSRTC=1.2 V
CKIL: VSRTC
0.1 F
Coin Cell
Battery
Main
Battery
CLK32KMCU
V
SRTC
&
Detect
On
Detect
Best of
Supply
On/Off
Button
V
COREDIG
32 kHz
Open Drain output for RTC wake-up
Processor
I/O
Core Supply
SOG Supply
SRTC
HP-RC
LP-RTC
32 kHz for
DSM timing