Datasheet

Analog Integrated Circuit Device Data
37 Freescale Semiconductor
MC34708
Functional Block Description
The following are text descriptions of the power states of the system for additional details of the state machine to complement
the drawing in Figure 6. Note that the SPI control is only possible in the Watchdog, On and User Off Wait states and the interrupt
line INT is kept low in all states except for Watchdog and On.
7.5.2.1 Coin Cell
The RTC module is powered from either the battery or the coin cell, due to insufficient voltage at VALWAYS, and the IC is not in
a Power Cut. No Turn On event is accepted in the Coin Cell state. Transition out (to the Off state) requires VALWAYS restoration
with a threshold above UVDET. RESETB and RESETBMCU are held low in this mode.
The RTC module remains active (32 kHz oscillator + RTC timers), along with VALWAYS level detection to qualify exit to the Off
state. VCOREDIG is off and the VDDLP regulator is on, the rest of the system is put into its lowest power configuration.
If the coin cell is depleted (VSTRC drops to 0.9 - 0.8 V while in the Coin Cell state), a complete system reset will occur. At next
power application / Turn On event, the system will startup reinitialized with all SPI bits including those that reset on RTCPORB
restored to their default states.
7.5.2.2 Off (with good battery)
If the supply VALWAYS is above the UVDET threshold, only the IC core circuitry at VCOREDIG and the RTC module are
powered, all other supplies are inactive. To exit the Off state, a valid turn on event is required. No specific timer is running in this
state. RESETB, RESETBMCU are held low in this state.
If the supply VALWAYS is below the UVDET threshold, no turn on events are accepted. If a valid coin cell is present, the core
gets powered from LICELL. The only active circuitry is the RTC module and the VCORE module powering VCOREDIG at 1.5 V.
7.5.2.3 Cold Start
Cold Start is entered upon a Turn On event from Off, Warm Boot, successful PCUT, or a Silent System Restart. The first 8.0 ms
is used for initialization which includes bias generation, PUMSx configuration latching, and qualification of the input supply level
BP. The switching and linear regulators are then powered up sequentially to limit the inrush current; see the Power Up section
for sequencing and default level details. The reset signals RESETB and RESETBMCU are kept low. The Reset timer starts
running when entering Cold Start. The Cold Start state is exited for the Watchdog state and both RESETB and RESETBMCU
become high (open drain output with external pull-ups) when the reset timer expires. The input control pins WDI, and STANDBY
are ignored.
7.5.2.4 Watchdog
The system is fully powered and under SPI/I
2
C control. RESETB and RESETBMCU are high. The Watchdog timer starts running
when entering the Watchdog state. When expired, the system transitions to the On state, where WDI will be checked and
monitored. The input control pins WDI and STANDBY are ignored while in the Watchdog state.
7.5.2.5 On Mode
The system is fully powered and under SPI control. RESETB and RESETBMCU are high. The WDI pin must be high to stay in
this state. The WDI IO supply voltage is referenced to SPIVCC (normally connected to SW5
= 1.8 V); SPIVCC must therefore
remain enabled to allow for proper WDI detection. If WDI goes low, the system will transition to the Off state or Cold Start
(depending on the configuration; refer to the section on Silent System Restart with WDI Event for details).
7.5.2.6 User Off Wait
The system is fully powered and under SPI control. The WDI pin no longer has control over the part. The Wait mode is entered
by a processor request for user off by setting the USEROFFSPI bit high. This is normally initiated by the end user via the power
key; upon receiving the corresponding interrupt, the system will determine if the product has been configured for User Off or
Memory Hold states (both of which first require passing through User Off Wait) or just transition to Off.
The Wait timer starts running when entering User Off Wait state. This leaves the processor time to suspend or terminate its tasks.
When expired, the Wait state is exited for User Off state or Memory Hold state depending on warm starts being enabled or not
via the WARMEN bit. The USEROFFSPI bit is being reset at this point by RESETB going low.