Datasheet
Analog Integrated Circuit Device Data
41 Freescale Semiconductor
MC34708
Functional Block Description
• Battery Attach: This occurs when BP crosses the LOWBATT threshold which is equivalent to attaching a charged battery to
the product.
• USB Attach: VBUS pulled high with corresponding interrupt and sense bits USBDET and USBDETS. This is equivalent to
plugging in a USB cable connected to a host powering the VBUS line. The battery voltage should be above LOWBATT. For
details on the USB detection, see
Mini/Micro USB Switch.
• RTC Alarm: TOD and DAY become equal to the alarm setting programmed. This allows powering up a product at a preset
time. BP should be above LOWBATT. For details and related interrupts, see Real Time Clock.
• System Restart: System restart which may occur after a system reset as described earlier in this section. This is an optional
function, see
Turn Off Events. BP should be above LOWBATT.
• Global System Reset: The global reset feature powers down the part, resets the SPI registers to their default value including
all the RTCPORB registers (except the DRM bit, and the RTC registers), and then powers back on. To enable a global reset,
the GLBRST pin needs to be pulled low for greater than GLBRSTTMR [1:0] seconds and then pulled back high (defaults to
12
s). BP should be above LOWBATT.
7.5.3.5 Turn Off Events
• Power Button Press (via WDI): User shutdown of a product is typically done by pressing the power button connected to the
PWRONx pin. This will generate an interrupt (PWRONxI), but will not directly power off the part. The product is powered off
by the processor’s response to this interrupt, which will be to pull WDI low. Pressing the power button is therefore, under
normal circumstances, not considered as a turn off event for the state machine. However, since the button press power down
is the most common turn off method for end products, it is described in this section as the product implementation for a WDI
initiated Turn Off event. Note that the software can configure a user initiated power down, via a power button press for
transition to a Low Power Off mode (Memory Hold or User Off) for a quicker restart than the default transition into the Off state.
• Power Button System Reset: A secondary application of the PWRONx pins is the option to generate a system reset. This is
recognized as a Turn Off event. By default, the system reset function is disabled but can be enabled by setting the
PWRONxRSTEN bits. When enabled, a four second long press on the power button will cause the device to go to the Off
mode, and as a result, the entire application will power down. An interrupt SYSRSTI is generated upon the next power up.
Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit.
• Thermal Protection: If the die gets overheated, the thermal protection will power off the part to avoid damage. A Turn On
event will not be accepted while the thermal protection is still being tripped. The part will remain in Off mode until cooling
sufficiently to accept a Turn On event. There are no specific interrupts related to this, other than the warning interrupts.
• BP lower than VBAT_TRKL: When the voltage at BP drops below VBAT_TRKL[1:0] - 100mV, the state machine will
transition to the Off mode. The SDWNB pin is used to notify the processor that the PMIC is going to immediately shutdown.
The PMIC will bring the SDWNB pin low for one 32
kHz clock cycle before powering down. This signal will then be brought
back high into the power off state.
Table 23. PWRONx Hardware Debounce Bit Settings
(39)
Bits State
Turn On
Debounce (ms)
Falling Edge INT
Debounce (ms)
Rising Edge INT
Debounce (ms)
PWRONxDBNC[1:0] 00 0.0 31.25 31.25
01 31.25 31.25 31.25
10 125 125 31.25
11 750 750 31.25
Notes
39. The sense bit PWRONxS is not debounced and follows the state of the PWRONx pin.
Table 24. Global Reset Time Settings
Bits State Time (s)
GLBRSTTMR[1:0] 00 INVALID
01 4
10 8
11 (default) 12