Datasheet

Analog Integrated Circuit Device Data
43 Freescale Semiconductor
MC34708
Functional Block Description
7.5.3.7 Power Monitoring
The voltage at BATT and BP are monitored by detectors as summarized in Table 27.
The UVDET and LOWBATT thresholds are related to the power on/off events as described earlier in this chapter. The LOWBATT
threshold when transitioned from low to a high is used to power on the MC34708. The LOWBATT threshold when transitioned
from high to low, is used as a low battery detect warning. An interrupt LOWBAT is generated when dropping below the high to
low threshold to indicate to the processor the battery is weak and a shutdown is imminent.
The LOWBATT detection threshold is debounced by the VBATTDB[2:0] SPI bits shown in Table 28.
7.5.3.8 Power Saving
7.5.3.8.1 System Standby
A product may be designed to go into DSM (Deep Sleep Mode) after periods of inactivity, the STANDBY pin is provided for board
level control of timing in and out of such deep sleep modes.
When a product is in DSM, it may be able to reduce the overall platform current by lowering the regulator output voltage, changing
the operating mode of the switching regulators or disabling some regulators. This can be obtained by controlling the STANDBY
pin. The configuration of the regulators in standby is pre-programmed through the SPI.
A lower power standby mode can be obtained by setting the ON_STBY_LP SPI bit to a one. With the ON_STBY_LP SPI bit set
and the STANDBY pin asserted a lower power standby will be entered. In the on Standby Low Power mode, the switching
Regulators should all be programmed into PFM mode and the LDO's should be configured to Low Power mode when the
STANDBY pin is asserted. The PLL is disabled in this mode so the mini USB will not be able to detect if an audio device, UART,
or a USB OTG device is attached. It will require the software to wake up occasionally to allow the mini-USB to detect if a device
Table 27. LOWBATT Detection Thresholds
Threshold in V
Bit setting
(40)
UVDET (V)
L to H transition
(Power on)
(41)
,
(42)
H to L transition
(Low battery detect)
(41)
,
(42)
LOWBATT1 LOWBATT0 LOWBATT LOWBATT
0 0 3.1 (Rising)
2.65 (Falling)
3.1 3.0
0 1 3.1 (Rising)
2.65 (Falling)
3.2 3.1
1 0 3.1 (Rising)
2.65 (Falling)
3.3 3.2
1 1 3.1 (Rising)
2.65 (Falling)
3.4 3.3
Notes
40. Default setting for LOWBATT[1:0] is 11.
41. The above specified thresholds are ±50 mV accurate for the indicated transition
42. A hysteresis is applied to the detectors on the order of 100 mV
Table 28. VBATTDB Debounce Times
VATTDB[1:0] Debounce Time
00 0 (default)
01 2 RTC clock cycles
10 4 RTC clock cycles
11 8 RTC clock cycles