Datasheet

Analog Integrated Circuit Device Data
47 Freescale Semiconductor
MC34708
Functional Block Description
7.5.4.2 Switching Frequency
A PLL generates the switching system clocking from the 32.768 kHz crystal oscillator reference. The switching frequency can be
programmed to 2.0 MHz or 4.0 MHz by setting the PLLX SPI bit as shown in Table 35.
The clocking system provides a near instantaneous activation when the Switching regulators are enabled or when exiting PFM
operation for PWM mode. The PLL can be configured for continuous operation with PLLEN = 1.
7.5.4.3 SW1
SW1 is fully integrated synchronous Buck PWM voltage mode control DC/DC regulator. It can be operated in single phase/dual
phase mode. The operating mode of the switching regulators is configured by the SW1CFG pin. The SW1CFG pin is sampled
at startup.
Figure 8. SW1 Single Phase Output Mode Block Diagram
Table 35. Buck Regulator Frequency
PLLX Switching Frequency (Hz)
0 2 000 000
1 4 000 000
Table 36. SW1 Configuration
SW1CFG SW1A/B Configuration Mode
VCOREDIG Single Phase Mode
Ground Dual Phase Mode
Driver
Contr oller
SW1IN
SW 1ALX
SW1FB
I
SEN SE
C
OSW1A
C
IN SW 1 A
L
SW 1A
SPI
Interface
GNDSW1A
SW1
SW1AMODE
SW1FAULT
BP
Driver
Contr oller
SW1BIN
SW 1BLX
I
SEN SE
C
IN SW 1B
GNDSW1B
SW1BMODE
SW1BFAULT
BP
SW1CFG
VCOREDIG
EA
Z1
Z2
Internal
Compensati on
V
REF
DAC
SPI
D
SW 1