Datasheet

Analog Integrated Circuit Device Data
65 Freescale Semiconductor
MC34708
Functional Block Description
7.5.6 Linear Regulators (LDOs)
This section describes the linear regulators provided. For convenience, these regulators are named to indicate their typical or
possible applications, but the supplies are not limited to these uses and may be applied to any loads within the specified regulator
capabilities.
A low power standby mode controlled by STANDBY is provided for the regulators with an external pass device in which the bias
current is aggressively reduced. This mode is useful for deep sleep operation, where certain supplies cannot be disabled, but
active regulation can be tolerated with lesser parametric requirements. The output drive capability and performance are limited
in this mode.
7.5.6.1 General Guidelines
The following applies to all linear regulators, unless otherwise specified.
• Parametric specifications assume the use of low ESR X5R/X7R ceramic capacitors with 20% accuracy and 15% temperature
spread, for a worst case stack up of 35% from the nominal value. Use of other types with wider temperature variation may
require a larger room temperature nominal capacitance value, to meet performance specs over temperature. Capacitor
derating as a function of DC bias voltage requires special attention. Minimum bypass capacitor guidelines are provided for
stability and transient performance. However, larger values may be applied, but performance metrics may be altered and
generally improved and should be confirmed in system applications.
• Regulators with an external PNP transistor require an equivalent resistance (including the ESR) in series with the output
capacitor, as noted in the specific regulator sections.
• Output voltage tolerance specified for each of the linear regulators include process variation, temperature range, static line
regulation, and static load regulation.
• In the Low-power mode, the output performance is degraded. Only those parameters listed in the Low-power mode section
are guaranteed. In this mode, the output current is limited to much lower levels than in the active mode.
• When a regulator gets disabled, the output will be pulled to ground by an internal pull-down. The pull-down is also activated
when RESETB goes low.
V
SWBST
TRANSIENT
Transient Load Response, IL from 100 to 1.0 mA in 1.0 µs
• Maximum transient Amplitude
- - 300
mV
V
SWBST
TRANSIENT
Transient Load Response, IL from 1.0 to 100 mA in 1.0 µs
• Time to settle 80% of transient
- - 500
µs
V
SWBST
TRANSIENT
Transient Load Response, IL from 100 to 1.0 mA in 1.0 µs
• Time to settle 80% of transient
- - 20
ms

SWBST
Efficiency, IL = IL
MAX
65 80 - %
I
SWBSTBIAS
Bias Current Consumption
• PFM or Auto mode
- 35 -
µA
I
LEAK-SWBST
NMOS Off Leakage
•SWBSTIN = 4.5 V, SWBSTMODE [1:0] = 0
- 1.0 6.0
µA
Notes:
57. V
IN
is the low side of the inductor connected to BP.
Table 53. SWBST Electrical Specifications
Characteristics noted under conditions BP = 3.6 V, V
BUS
= 5.0 V, - 40 C  T
A
 85 C, unless otherwise noted. Typical values
at BP = 3.6 V and T
A
= 25 °C under nominal conditions, unless otherwise noted.
Symbol Characteristic Min Typ Max Unit Notes